Datasheet
2
AD7714
REV. C
–7–
ORDERING GUIDE
AV
DD
Temperature Package
Model Supply Range Option*
AD7714AN-5 5 V –40°C to +85°C N-24
AD7714AR-5 5 V –40°C to +85°C R-24
AD7714ARS-5 5 V –40°C to +85°C RS-28
AD7714AN-3 3 V –40°C to +85°C N-24
AD7714AR-3 3 V –40°C to +85°C R-24
AD7714ARS-3 3 V –40°C to +85°C RS-28
AD7714YN 3 V/5 V –40°C to +105°C N-24
AD7714YR 3 V/5 V –40°C to +105°C R-24
AD7714YRU 3 V/5 V –40°C to +105°C RU-24
AD7714AChips-5 5 V –40°C to +85°CDie
AD7714AChips-3 3 V –40°C to +85°CDie
EVAL-AD7714-5EB 5 V Evaluation Board
EVAL-AD7714-3EB 3 V Evaluation Board
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +2.7 V to +5.25 V; AGND = DGND = 0 V; f
CLKIN
= 2.5␣ MHz; Input Logic 0 = 0 V,
Logic 1 = DV
DD
unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter (A, Y Versions) Units Conditions/Comments
f
CLKIN
3, 4
400 kHz min Master Clock Frequency: Crystal/Resonator or Externally
Supplied
2.5 MHz max For Specified Performance
t
CLK IN LO
0.4 × t
CLK IN
ns min Master Clock Input Low Time. t
CLK IN
= 1/f
CLK IN
t
CLK IN HI
0.4 × t
CLK IN
ns min Master Clock Input High Time
t
DRDY
500 × t
CLK IN
ns nom DRDY High Time
t
1
100 ns min SYNC Pulsewidth
t
2
100 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min DRDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
5
t
5
6
0 ns min SCLK Active Edge to Data Valid Delay
5
80 ns max DV
DD
= +5␣ V
100 ns max DV
DD
= +3␣ V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Active Edge Hold Time
5
t
9
7
10 ns min Bus Relinquish Time after SCLK Active Edge
5
60 ns max DV
DD
= +5␣ V
100 ns max DV
DD
= +3␣ V
t
10
100 ns max SCLK Active Edge to DRDY High
5, 8
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
5
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
20 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 6 and 7. Timing applies for all grades.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7714 is production tested with f
CLKIN
at 2.4576␣ MHz (1␣ MHz for some I
DD
tests). It is guaranteed by characterization to operate at 400␣ kHz.
5
SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
7
These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
8
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
TO OUTPUT
PIN
50pF
I
SINK
(800mA AT DV
DD
= +5V
100mA AT DV
DD
= +3.3V)
+1.6V
I
SOURCE
(200mA AT DV
DD
= +5V
100mA AT DV
DD
= +3.3V)