Datasheet

AD7714–SPECIFICATIONS
Parameter A Versions Units Conditions/Comments
TRANSDUCER BURNOUT
14
Current 1 µA nom
Initial Tolerance ±10 % typ
Drift 0.1 %/°C typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
15
–(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
16
–(1.05 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
16
0.8 × V
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1 × V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage (AD7714-3) +3 to +3.6 V For Specified Performance
AV
DD
Voltage (AD7714-5) +4.75 to +5.25 V For Specified Performance
DV
DD
Voltage +3 to +5.25 V For Specified Performance
Power Supply Currents
AV
DD
Current AV
DD
= 3.3␣ V or 5␣ V. BST Bit of Filter High Register = 0
17
0.27 mA max Typically 0.2 mA. BUFFER = 0 V. f
CLK IN
= 1␣ MHz or 2.4576␣ MHz
0.6 mA max Typically 0.4 mA. BUFFER = DV
DD
. f
CLK IN
= 1␣ MHz or 2.4576␣ MHz
AV
DD
= 3.3␣ V or 5␣ V. BST Bit of Filter High Register = 1
17
0.5 mA max Typically 0.3␣ mA. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz
1.1 mA max Typically 0.8␣ mA. BUFFER = DV
DD
. f
CLK IN
= 2.4576␣ MHz
DV
DD
Current
18
Digital I/Ps = 0␣ V or DV
DD.
External MCLK IN
0.23 mA max Typically 0.15␣ mA. DV
DD
= 3.3␣ V. f
CLK IN
= 1␣ MHz
0.4 mA max Typically 0.3␣ mA. DV
DD
= 5␣ V. f
CLK IN
= 1␣ MHz
0.5 mA max Typically 0.4␣ mA. DV
DD
= 3.3␣ V. f
CLK IN
= 2.4576␣ MHz
0.8 mA max Typically 0.6␣ mA. DV
DD
= 5␣ V. f
CLK IN
= 2.4576␣ MHz
Power Supply Rejection
19
See Note 20 dB typ
Normal-Mode Power Dissipation
18
AV
DD
= DV
DD
= +3.3␣ V. Digital I/Ps = 0␣ V or DV
DD
. External MCLK IN
1.65 mW max Typically 1.25␣ mW. BUFFER = 0␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
2.75 mW max Typically 1.8␣ mW. BUFFER = +3.3␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
2.55 mW max Typically 2␣ mW. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
3.65 mW max Typically 2.6␣ mW. BUFFER = +3.3␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
Normal-Mode Power Dissipation AV
DD
= DV
DD
= +5␣ V. Digital I/Ps = 0␣ V or DV
DD
. External MCLK IN
3.35 mW max Typically 2.5␣ mW. BUFFER = 0␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
5 mW max Typically 3.5␣ mW. BUFFER = +5␣ V. f
CLK IN
= 1␣ MHz. BST Bit = 0
5.35 mW max Typically 4␣ mW. BUFFER = 0␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
7 mW max Typically 5␣ mW. BUFFER = +5␣ V. f
CLK IN
= 2.4576␣ MHz. BST Bit = 0
Standby (Power-Down) Current
21
40 µA max External MCLK IN = 0 V or DV
DD
. Typically 20␣ µA. V
DD
= +5 V
Standby (Power-Down) Current
21
10 µA max External MCLK IN = 0 V or DV
DD
. Typically 5␣ µA. V
DD
= +3.3 V
NOTES
15
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30␣ mV or go more negative than AGND␣ –␣ 30␣ mV. The
offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17
For higher gains (≥8) at f
CLK␣ IN
= 2.4576␣ MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the crystal
or resonator type (see Clocking and Oscillator Circuit section).
19
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20
PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.
21
If the external master clock continues to run in standby mode, the standby current increases to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. When
using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
Specifications subject to change without notice.
(AV
DD
= + 3.3␣ V to +5␣ V, DV
DD
= +3.3␣ V to +5␣ V, REF IN(+) = +1.25␣ V (AD7714-3) or +2.5␣ V
(AD7714-5); REF␣ IN(–) = AGND; MCLK␣ IN = 1␣ MHz to 2.4576␣ MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. C–4–