Datasheet

REV. D–4–
AD7713
Parameter A, S Versions
1
Unit Conditions/Comments
AIN3
Positive Full-Scale Calibration Limit
13
+(4.2 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain
(Between 1 and 128).
Offset Calibration Limit
15
0 to V
REF
/GAIN V max GAIN Is the Selected PGA Gain
(Between 1 and 128).
Input Span +(3.2 ⫻ V
REF
)/GAIN V min GAIN Is the Selected PGA Gain
(Between 1 and 128).
+(4.2 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain
(Between 1 and 128).
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
16
5 to 10 V nom ±5% for Specified Performance.
DV
DD
Voltage
17
5V nom ±5% for Specified Performance.
Power Supply Currents
AV
DD
Current 0.6 mA max AV
DD
= 5 V.
0.7 mA max AV
DD
= 10 V.
DV
DD
Current 0.5 mA max f
CLK IN
= 1 MHz.
Digital Inputs 0 V to DV
DD
.
1 mA max f
CLK IN
= 2 MHz.
Digital Inputs 0 V to DV
DD
.
Power Supply Rejection
18
Rejection w.r.t. AGND.
(AV
DD
and DV
DD
)
19
dB typ
Power Dissipation
Normal Mode 5.5 mW max AV
DD
= DV
DD
= 5 V, f
CLK IN
= 1 MHz;
Typically 3.5 mW.
Standby (Power-Down) Mode 300 µW max AV
DD
= DV
DD
= 5 V, Typically 150 µW.
NOTES
1
Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recom-
mended source resistance depends on the selected gain.
8
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage
range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AV
DD
+ 30 mV or more
negative than AGND – 30 mV.
9
V
REF
= REF IN(+) – REF IN(–).
10
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and AGND – 30 mV.
11
This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section of the specifications.
12
Guaranteed by design, not production tested.
13
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
14
These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV
DD
+ 30 mV or go more negative than
AGND – 30 mV.
15
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16
Operating with AV
DD
voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range.
17
The ± 5% tolerance on the DV
DD
input is allowed provided that DV
DD
does not exceed AV
DD
by more than 0.3 V.
18
Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz.
19
PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.