Datasheet

REV. F
AD7712
–5–
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Unit Conditions/Comments
f
CLK IN
4, 5
Master Clock Frequency: Crystal Oscillator or
Externally Supplied
400 kHz min AV
DD
= 5 V ± 5%
10 MHz max For Specified Performance
8 MHz AV
DD
= 5.25 V to 10.5 V
t
CLK IN LO
0.4 ⫻ t
CLK IN
ns min Master Clock Input Low Time; t
CLK IN
= 1/f
CLK IN
t
CLK IN HI
0.4 ⫻ t
CLK IN
ns min Master Clock Input High Time
t
r
6
50 ns max Digital Output Rise Time; Typically 20 ns
t
f
6
50 ns max Digital Output Fall Time; Typically 20 ns
t
1
1000 ns min SYNC Pulse Width
Self-Clocking Mode
t
2
0 ns min DRDY to RFS Setup Time; t
CLK IN
= 1/f
CLK IN
t
3
0 ns min DRDY to RFS Hold Time
t
4
2 ⫻ t
CLK IN
ns min A0 to RFS Setup Time
t
5
0 ns min A0 to RFS Hold Time
t
6
4 ⫻ t
CLK IN
+ 20 ns max RFS Low to SCLK Falling Edge
t
7
7
4 ⫻ t
CLK IN
+ 20 ns max Data Access Time (RFS Low to Data Valid)
t
8
7
t
CLK IN
/2 ns min SCLK Falling Edge to Data Valid Delay
t
CLK IN
/2 + 30 ns max
t
9
t
CLK IN
/2 ns nom SCLK High Pulse Width
t
10
3 ⫻ t
CLK IN
/2 ns nom SCLK Low Pulse Width
t
14
50 ns min A0 to TFS Setup Time
t
15
0 ns min A0 to TFS Hold Time
t
16
4 ⫻ t
CLK IN
+ 20 ns max TFS to SCLK Falling Edge Delay Time
t
17
4 ⫻ t
CLK IN
ns min TFS to SCLK Falling Edge Hold Time
t
18
0 ns min Data Valid to SCLK Setup Time
t
19
10 ns min Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 11 to 14.
3
The AD7712 is specified with a 10 MHz clock for AV
DD
voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
5
The AD7712 is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
< 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
(DV
DD
= +5 V ⴞ 5%; AV
DD
= +5 V or +10 V
3
ⴞ 5%; V
SS
= 0 V or –5 V ⴞ 5%; AGND = DGND =
0 V; f
CLKIN
=10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
TIMING CHARACTERISTICS
1, 2