Datasheet

REV. F
AD7712
–3–
SPECIFICATIONS (continued)
Parameter A, S Versions
1
Unit Conditions/Comments
REFERENCE OUTPUT
Output Voltage 2.5 V nom
Initial Tolerance ±1% max
Drift 20 ppm/°C typ
Output Noise 30 µV typ pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth
Line Regulation (AV
DD
)1 mV/V max
Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA
External Current 1 mA max
V
BIAS
INPUT
13
Input Voltage Range AV
DD
– 0.85 ⫻ V
REF
See V
BIAS
Input Section
or AV
DD
– 3.5 V max Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or AV
DD
– 2.1 V max Whichever Is Smaller: +5 V/0 V Nominal AV
DD
/V
SS
V
SS
+ 0.85 ⫻ V
REF
See V
BIAS
Input Section
or V
SS
+ 3 V min Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or V
SS
+ 2.1 V min Whichever Is Greater: +5 V/0 V Nominal AV
DD
/V
SS
V
BIAS
Rejection 65 to 85 dB typ Increasing with Gain
LOGIC INPUTS
Input Current ±10 µA max
All Inputs except MCLK IN
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 2.0 V min
MCLK IN Only
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 3.5 V min
LOGIC OUTPUTS
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 1.6 mA
V
OH
, Output High Voltage 4.0 V min I
SOURCE
= 100 µA
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance
14
9 pF typ
TRANSDUCER BURNOUT
Current 4.5 µA nom
Initial Tolerance ±10 % typ
Drift 0.1 %/°C typ
SYSTEM CALIBRATION
AIN1
Positive Full-Scale Calibration Limit
15
(1.05 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
15
–(1.05 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
16, 17
–(1.05 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
15
0.8 ⫻ V
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
AIN2
Positive Full-Scale Calibration Limit
15
(4.2 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
15
–(4.2 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
17
–(4.2 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
15
3.2 ⫻ V
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
(8.4 ⫻ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
13
The AD7712 is tested with the following V
BIAS
voltages. With AV
DD
= 5 V and V
SS
= 0 V, V
BIAS
= 2.5 V; with AV
DD
= 10 V and V
SS
= 0 V, V
BIAS
= 5 V and
with AV
DD
= 5 V and V
SS
= –5 V, V
BIAS
= 0 V.
14
Guaranteed by design, not production tested.
15
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
16
These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AV
DD
+ 30 mV or does not go more negative
than V
SS
– 30 mV.
17
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.