Datasheet

Parameter A, S Versions
1
Unit Conditions/Comments
V
BIAS
INPUT
12
Input Voltage Range AV
DD
– 0.85 ¥ V
REF
See V
BIAS
Input Section
or AV
DD
– 3.5 V max Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or AV
DD
– 2.1 V max Whichever Is Smaller: +5 V/0 V Nominal AV
DD
/V
SS
V
SS
+ 0.85 ¥ V
REF
See V
BIAS
Input Section
or V
SS
+ 3 V min Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or V
SS
+ 2.1 V min Whichever Is Greater: +5 V/0 V Nominal AV
DD
/V
SS
V
BIAS
Rejection 65 to 85 dB typ Increasing with Gain
LOGIC INPUTS
Input Current ± 10 mA max
All Inputs except MCLK IN
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 2.0 V min
MCLK IN Only
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 3.5 V min
LOGIC OUTPUTS
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 1.6 mA
V
OH
, Output High Voltage DV
DD
– 1 V min I
SOURCE
= 100 mA
Floating State Leakage Current ± 10 mA max
Floating State Output Capacitance
13
9 pF typ
TRANSDUCER BURNOUT
Current 4.5 mA nom
Initial Tolerance @ 25∞C ± 10 % typ
Drift 0.1 %/∞C typ
RTD EXCITATION CURRENT
Output Current 400 mA nom
Initial Tolerance @ 25∞C ± 20 % max
Drift 20 ppm/∞C typ
Line Regulation (AV
DD
) 400 nA/V max AV
DD
= 5 V
Load Regulation 400 nA/V max
Output Compliance AV
DD
– 2 V max
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
14
–(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
15
–(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
15
0.8 ¥ V
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12
The AD7711A is tested with the following V
BIAS
voltages. With AV
DD
= 5 V and V
SS
= 0 V, V
BIAS
= 2.5 V, with AV
DD
= 10 V and V
SS
= 0 V, V
BIAS
= 5 V, and with
AV
DD
= 5 V and V
SS
= –5 V, V
BIAS
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7711A
–3–
REV. D