Datasheet

REV. D
AD7711A
–26–
Table VIII. 8XC51 Code for Writing to the AD7711A
MOV SCON,#00000000B; Configure 8051 for MODE 0
Operation & Enable Serial Reception
MOV IE,#10010000B; Enable Transmit Interrupt
MOV IP,#00010000B; Prioritize the Transmit Interrupt
SETB 91H; Bring TFS High
SETB 90H; Bring RFS High
MOV R1,#003H; Sets Number of Bytes to Be Written
in a Write Operation
MOV R0,#030H; Start Address in RAM for Bytes
MOV A,#00H; Clear Accumulator
MOV SBUF,A; Initialize the Serial Port
WAIT:
JMP WAIT; Wait for Interrupt
INT ROUTINE:
NOP; Interrupt Subroutine
MOV A,R1; Load R1 to Accumulator
JZ FIN; If Zero Jump to FIN
DEC R1; Decrement R1 Byte Counter
MOV A,@R; Move Byte into the Accumulator
INC R0; Increment Address
RLC A; Rearrange Data—From LSB First
to MSB First
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C:MOV A,B;
CLR 93H; Bring A0 Low
CLR 91H; Bring TFS Low
MOV SBUF,A; Write to Serial Port
RETI; Return from Subroutine
FIN:
SETB 91H; Set TFS High
SETB 93H; Set A0 High
RETI; Return from Interrupt Subroutine
AD7711A to 68HC11 Interface
Figure 18 shows an interface between the AD7711A and the
68HC11 microcontroller. The AD7711A is configured for its
external clocking mode while the SPI port is used on the 68HC11,
which is in its single chip mode. The DRDY line from the
AD7711A is connected to the Port PC2 input of the 68HC11,
so the DRDY line is polled by the 68HC11. The DRDY line
can be connected to the IRQ input of the 68HC11 if an inter-
rupt driven system is preferred. The 68HC11 MOSI and MISO
lines should be configured for wired-OR operation. Depending
on the interface configuration, it may be necessary to provide
bidirectional buffers between the 68HC11 MOSI and MISO
lines.
The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 0 and its CPHA bit set to a Logic 1. With a
10 MHz master clock on the AD7711A, the interface will oper-
ate with all four serial clock rates of the 68HC11.
AD7711A
SDATA
SCLK
A0
RFS
TFS
PC0
MISO
SCK
PC1
PC2
MODE
PC3
DRDY
SYNC
68HC11
MOSI
SS
DV
DD
DV
DD
Figure 18. AD7711A to 68HC11 Interface