Datasheet

2
AD7711A
–25–REV. D
START
WRITE DATA FROM
ACCUMULATOR TO
SERIAL BUFFER
BRING
TFS AND A0
LOW
LOAD DATA FROM
ADDRESS TO
ACCUMULATOR
CONFIGURE AND
INITIALIZE ␮C/␮P
SERIAL PORT
BRING
RFS, TFS AND
A0 HIGH
BRING
TFS AND A0
HIGH
END
ⴛ3
REVERSE
ORDER OF
BITS
Figure 16. Flowchart for Single Write Operation
to the AD7711A
AD7711A–8051 Interface
Figure 17 shows an interface between the AD7711A and the
8XC51 microcontroller. The AD7711A is configured for its exter-
nal clocking mode, while the 8XC51 is configured in its Mode 0
serial interface mode. The DRDY line from the AD7711A is
connected to the Port P1.2 input of the 8XC51, so the DRDY
P1.0
P3.0
P3.1
P1.1
P1.2
P1.3
8XC51
AD7711A
SDATA
A0
RFS
TFS
MODE
DRDY
SYNC
SCLK
DV
DD
Figure 17. AD7711A to 8XC51 Interface
line is polled by the 8XC51. The DRDY line can be connected
to the INT1 input of the 8XC51 if an interrupt driven system is
preferred.
Table VII shows some typical 8XC51 code used for a single
24-bit read from the output register of the AD7711A. Table VIII
shows some typical code for a single write operation to the con-
trol register of the AD7711A. The 8XC51 outputs the LSB first
in a write operation while the AD7711A expects the MSB first
so the data to be transmitted has to be rearranged before being
written to the output serial register. Similarly, the AD7711A
outputs the MSB first during a read operation while the 8XC51
expects the LSB first. Therefore, the data read into the serial
buffer needs to be rearranged before the correct data-word from
the AD7711A is available in the accumulator.
Table VII. 8XC51 Code for Reading from the AD7711A
MOV SCON,#00010001B; Configure 8051 for MODE 0
Operation
MOV IE,#00010000B; Disable All Interrupts
SETB 90H; Set P1.0, Used as RFS
SETB 91H; Set P1.1, Used as TFS
SETB 93H; Set P1.3, Used as A0
MOV R1,#003H; Sets Number of Bytes to Be Read in
A Read Operation
MOV R0,#030H; Start Address for Where Bytes Will
Be Loaded
MOV R6,#004H; Use P1.2 as DRDY
WAIT:
NOP;
MOV A,P1; Read Port 1
ANL A,R6; Mask Out All Bits Except DRDY
JZ READ; If Zero Read
SJMP WAIT; Otherwise Keep Polling
READ:
CLR 90H; Bring RFS Low
CLR 98H; Clear Receive Flag
POLL:
JB 98H, READ1 Tests Receive Interrupt Flag
SJMP POLL
READ 1:
MOV A,SBUF; Read Buffer
RLC A; Rearrange Data
MOV B.0,C; Reverse Order of Bits
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A; Write Data to Memory
INC R0; Increment Memory Location
DEC R1 Decrement Byte Counter
MOV A,Rl
JZ END Jump if Zero
JMP WAIT Fetch Next Byte
END:
SETB 90H Bring RFS High
FIN:
SJMP FIN