Datasheet

AD7711A

–23–REV. D

this SCLK signal with the MSB transferred first. On the last

active high time of SCLK, the LSB is loaded to the AD7711A.

Figure 13b shows a timing diagram for a write operation to the

AD7711A with TFS returning high during the write operation

and returning low again to write the rest of the data-word. Tim-

ing parameters and functions are very similar to that outlined for

Figure 13a, but Figure 13b has a number of additional times to

show timing relationships when TFS returns high in the middle

of transferring a word.

Data to be loaded to the AD7711A must be valid prior to the

rising edge of the SCLK signal. TFS should return high during

the low time of SCLK. After TFS returns low again, the next bit

of the data-word to be loaded to the AD7711A is clocked in on

next high level of the SCLK input. On the last high time of the

SCLK input, the LSB is loaded to the AD7711A.

Write Operation

Data can be written to either the control register or calibration

DRDY line, and the write operation does not have any effect

on the status of DRDY. A write operation to the control register

or the calibration register must always write 24 bits to the

respective register.

Figure 13a shows a write operation to the AD7711A with TFS

remaining low for the duration of the write operation. A0 deter-

mines whether a write operation transfers data to the control

remain valid for the duration of the serial write operation. As

before, the serial clock line should be low between read and

write operations. The serial data to be loaded to the AD7711A

must be valid on the high level of the externally applied SCLK

signal. Data is clocked into the AD7711A on the high level of

MSB

LSB

SDATA (I)

SCLK (I)

TFS (I)

A0 (I)

Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation

SDATA (I)

SCLK (I)

TFS (I)

A0 (I)

MSB BIT N BIT N+1

Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation

(

TFS

Returns High during Write Operation)