Datasheet

REV. G
–6–
AD7710
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Unit Conditions/Comments
External Clocking Mode
f
SCLK
f
CLK IN
/5 MHz max Serial Clock Input Frequency
t
20
0 ns min DRDY to RFS Setup Time
t
21
0 ns min DRDY to RFS Hold Time
t
22
2 × t
CLK IN
ns min A0 to RFS Setup Time
t
23
0 ns min A0 to RFS Hold Time
t
24
7
4 × t
CLK IN
ns max Data Access Time (RFS Low to Data Valid)
t
25
7
10 ns min SCLK Falling Edge to Data Valid Delay
2 × t
CLK IN
+ 20 ns max
t
26
2 × t
CLK IN
ns min SCLK High Pulse Width
t
27
2 × t
CLK IN
ns min SCLK Low Pulse Width
t
28
t
CLK IN
+ 10 ns max SCLK Falling Edge to DRDY High
t
29
8
10 ns min SCLK to Data Valid Hold Time
t
CLK IN
+ 10 ns max
t
30
10 ns min RFS/TFS to SCLK Falling Edge Hold Time
t
31
8
5 × t
CLK IN
/2 + 50 ns max RFS to Data Valid Hold Time
t
32
0 ns min A0 to TFS Setup Time
t
33
0 ns min A0 to TFS Hold Time
t
34
4 × t
CLK IN
ns min SCLK Falling Edge to TFS Hold Time
t
35
2 × t
CLK IN
– SCLK High ns min Data Valid to SCLK Setup Time
t
36
30 ns min Data Valid to SCLK Hold Time
NOTES
8
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
PIN CONFIGURATION
DIP AND SOIC
SCLK
MCLK IN
DGND
DV
DD
MODE
AIN1(+) AGND
MCLK OUT
A0
SDATA
AIN1(–)
I
OUT
REF OUT
REF IN(+)
REF IN(–)
AV
DD
V
BIAS
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
11
12
13
AD7710
SYNC
V
SS
DRDY
RFS
TFS
AIN2(+)
AIN2(–)
TO OUTPUT
PIN
+2.1V
1.6mA
200␮A
100pF
Figure 1. Load Circuit for Access Time and
Bus Relinquish Time