Datasheet

REV. G
–12–
AD7710
1k
10
0.1
10 1k 10k
100
1
100
NOTCH FREQUENCY – Hz
OUTPUT NOISE – ␮V
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
Figure 2b. Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
The basic connection diagram for the part is shown in Figure 3.
This figure shows the AD7710 in the external clocking mode
with both the AV
DD
and DV
DD
pins being driven from the ana-
log 5 V supply. Some applications have separate supplies for
both AV
DD
and DV
DD
, and in some cases, the analog supply
exceeds the 5 V digital supply (see the Power Supplies and
Grounding section).
REF IN(+)
REF OUT
AIN1(+)
AIN1(–)
AIN2(+)
AGND
DGND
MCLK IN
MCLK OUT
MODE
SCLK
SDATA
DRDY
TFS
RFS
REF IN(–)
V
BIAS
SYNC
A0
DIFFERENTIAL
ANALOG INPUT
ANALOG
GROUND
DIGITAL
GROUND
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
+5V
AD7710
10␮F
0.1␮F
0.1␮F
ANALOG
+5V SUPPLY
AV
DD
DV
DD
V
SS
I
OUT
AIN2(–)
DIFFERENTIAL
ANALOG INPUT
Figure 3. Basic Connection Diagram
Figure 2 show information similar to that outlined in Table I. In this plot, however, the output rms noise is shown for the full range
of available cutoffs frequencies. The numbers given in these plots are typical values at 25°C.
10k
100
0.1
10 1k 10k
1k
10
1
100
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
NOTCH FREQUENCY – Hz
OUTPUT NOISE – ␮V
Figure 2a. Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
CIRCUIT DESCRIPTION
The AD7710 is a sigma-delta A/D converter with on-chip digital
filtering for measuring wide dynamic range, low frequency sig-
nals in applications such as weigh scale, industrial control, or
process control. It contains a sigma-delta (or charge-balancing)
ADC, a calibration microcontroller with on-chip static RAM, a
clock oscillator, a digital filter, and a bidirectional serial commu-
nications port.
The part contains two programmable gain differential analog
input channels. The gain range is from 1 to 128 allowing the
part to accept unipolar signals of 0 mV to 20 mV and 0 V to
2.5 V, or bipolar signals in the range of ± 20 mV to ±2.5 V when
the reference input voltage equals 2.5 V. The input signal to the
selected analog input channel is continuously sampled at a rate
determined by the frequency of the master clock, MCLK IN,
and the selected gain (see Table III). A charge-balancing A/D
converter (sigma-delta modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc
3
digital low-pass filter processes the output of the
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of the filter. The output
data can be read from the serial port randomly or periodically at
any rate up to the output register update rate. The first notch of
this digital filter (and therefore its –3 dB frequency) can be
programmed via an on-chip control register. The programmable
range for this first notch frequency is 9.76 Hz to 1.028 kHz,
giving a programmable range for the –3 dB frequency of 2.58 Hz
to 269 Hz.