Datasheet

REV. A
AD7709
–6–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A, B Version) Unit Conditions/Comments
t
1
30.5176 ms typ Crystal Oscillator Period
t
2
50 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min RDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
5
4
0 ns min SCLK Active Edge to Data Valid Delay
3
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
5A
4, 5
0 ns min CS Falling Edge to Data Valid Delay
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
3
t
9
6
10 ns min Bus Relinquish Time after SCLK Inactive Edge
3
80 ns max
t
10
100 ns max SCLK Active Edge to RDY High
3, 7
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
25 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 2 and 3.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish
times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; X
TAL
= 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = V
DD
unless otherwise noted.)