Datasheet

REV. 0
AD7708/AD7718
–9–
TIMING CHARACTERISTICS
1, 2
(AV
DD
= 2.7 V to 3.6 V or AV
DD
= 5 V ⴞ 5%; DV
DD
= 2.7 V to 3.6 V or DV
DD
= 5 V ⴞ 5%; AGND =
DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.
Limit at T
MIN
, T
MAX
Parameter (B Version) Unit Conditions/Comments
t
1
32.768 kHz typ Crystal Oscillator Frequency
t
2
50 ns min RESET Pulsewidth
Read Operation
t
3
0 ns min RDY to CS Setup Time
t
4
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
5
4
0 ns min SCLK Active Edge to Data Valid Delay
3
60 ns max DV
DD
= 4.5 V to 5.5 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
5A
4, 5
0 ns min CS Falling Edge to Data Valid Delay
3
60 ns max DV
DD
= 4.5 V to 5.5 V
80 ns max DV
DD
= 2.7 V to 3.6 V
t
6
100 ns min SCLK High Pulsewidth
t
7
100 ns min SCLK Low Pulsewidth
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
3
t
9
6
10 ns min Bus Relinquish Time after SCLK Inactive Edge
3
80 ns max
t
10
100 ns max SCLK Active Edge to RDY High
3, 7
Write Operation
t
11
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
3
t
12
30 ns min Data Valid to SCLK Edge Setup Time
t
13
25 ns min Data Valid to SCLK Edge Hold Time
t
14
100 ns min SCLK High Pulsewidth
t
15
100 ns min SCLK Low Pulsewidth
t
16
0 ns min CS Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage
level of 1.6 V.
2
See Figures 1 and 2.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.
7
RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
TO OUTPUT
PIN
50pF
I
SINK
I
SOURCE
1.6V
(1.6mA WITH DV
DD
= 5V
100␮A WITH DV
DD
= 3V)
(200␮A WITH DV
DD
= 5V
100␮A WITH DV
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization