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ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 28

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may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

AD7708/AD7718

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

8-/10-Channel, Low Voltage,

Low Power, ⌺-⌬ ADCs

FUNCTIONAL BLOCK DIAGRAM

DVDD XTAL1 XTAL2

MUX

POS BUF

⌺-⌬ ADC*

AIN1

AIN2

AIN3

AIN4

PGA

OSC

AND

PLL

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DOUT

DIN

SCLK

RDY

RESET

AV DD

I/O PORT

AV DD

AD7708/ AD7718

DGND

P2 P1

REFIN2(+)/AIN9 REFIN1(+) REFIN2(–)/AIN10 REFIN1(–)

AINCOM

AIN5

AIN6

AIN7

AIN8

AGND

*AD7708 16-BIT ADC

*AD7718 24-BIT ADC

REFIN(+) REFIN(–)

NEG BUF

FEATURES

8-/10-Channel, High Resolution ⌺-⌬ ADCs

AD7708 Has 16-Bit Resolution

AD7718 Has 24-Bit Resolution

Factory-Calibrated

Single Conversion Cycle Setting

Programmable Gain Front End

Simultaneous 50 Hz and 60 Hz Rejection

VREF Select

™ Allows Absolute and Ratiometric

Measurement Capability

Operation Can Be Optimized for

Analog Performance (CHOP = 0) or

Channel Throughput (CHOP = 1)

INTERFACE

3-Wire Serial

SPI

, QSPI

, MICROWIRE

, and DSP-Compatible

Schmitt Trigger on SCLK

POWER

Specified for Single 3 V and 5 V Operation

Normal: 1.28 mA Typ @ 3 V

Power-Down: 30 ␮A (32 kHz Crystal Running)

On-Chip Functions

Rail-to-Rail Input Buffer and PGA

2-Bit Digital I/O Port

APPLICATIONS

Industrial Process Control

Instrumentation

Pressure Transducers

Portable Instrumentation

Smart Transmitters

SPI and QSPI are trademarks of Motorola Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

VREF Select is a trademark of Analog Devices, Inc.

GENERAL DESCRIPTION

The AD7708/AD7718 are complete analog front-ends for low

frequency measurement applications. The AD7718 contains a

24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully-

differential input channels or 8/10 pseudo-differential input

channels. Two pins on the device are configurable as analog

inputs or reference inputs. The AD7708 is a 16-bit version of

the AD7718. Input signal ranges from 20 mV to 2.56 V can be

directly converted using these ADCs. Signals can be converted

directly from a transducer without the need for signal conditioning.

The device operates from a 32 kHz crystal with an on-board PLL

generating the required internal operating frequency. The output

data rate from the part is software programmable. The peak-to-

peak resolution from the part varies with the programmed gain

and output data rate.

The part operates from a single 3 V or 5 V supply. When operating

from 3 V supplies, the power dissipation for the part is 3.84 mW typ.

Both parts are pin-for-pin compatible allowing an upgradable

path from 16 to 24 bits without the need for hardware modifica-

tions. The AD7708/AD7718 are housed in 28-lead SOIC and

TSSOP packages.

Summary of content (44 pages)

PAGE 1
a 8-/10-Channel, Low Voltage, Low Power, ⌺-⌬ ADCs AD7708/AD7718 GENERAL DESCRIPTION FEATURES 8-/10-Channel, High Resolution ⌺-⌬ ADCs AD7708 Has 16-Bit Resolution AD7718 Has 24-Bit Resolution Factory-Calibrated Single Conversion Cycle Setting Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection VREF Select™ Allows Absolute and Ratiometric Measurement Capability Operation Can Be Optimized for Analog Performance (CHOP = 0) or Channel Throughput (CHOP = 1) The AD7708/AD7718 are complete analog
PAGE 2
AD7708/AD7718 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 User Nonprogrammable Test Registers . . . . . . . . . . . . . . . . 31 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . . 32 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AD7718 SPECIFICATIONS . . . . . . .
PAGE 3
AD7708/AD7718 AD7718 SPECIFICATIONS1 (AV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications TMIN to TMAX unless otherwise noted.) Parameter B Grade Unit Test Conditions Hz min kHz max Bits min Bits p-p Bits p-p CHOP = 1 Integral Nonlinearity Offset Error3 16.06 1.
PAGE 4
1 (AV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = AD7718–SPECIFICATIONS 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T to T unless otherwise noted.) DD DD MIN Parameter AD7718 (CHOP ENABLED) Output Update Rate No Missing Codes2 Resolution Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temp4 Full-Scale Error3 Gain Drift vs.
PAGE 5
AD7708/AD7718 Parameter LOGIC INPUTS (Continued) SCLK Only (Schmitt-Triggered Input)2 VT(+) VT(–) VT(+) – VT(–) VT(+) VT(–) VT(+)–VT(–) XTAL1 Only2 VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage Input Currents Input Capacitance LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating State Leakage Current Floating State Output Capacitance Data Output Coding B Grade Unit
PAGE 6
AD7708/AD7718 AD7708 SPECIFICATIONS1 (AV DD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications TMIN to TMAX unless otherwise noted.) Parameter AD7708 (CHOP DISABLED) Output Update Rate No Missing Codes2 Resolution Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temp4 Full-Scale Error3 Gain Drift vs.
PAGE 7
AD7708/AD7718 Parameter AD7708 (CHOP ENABLED) Output Update Rate No Missing Codes2 Resolution Output Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temp4 Full-Scale Error3 Gain Drift vs. Temp4 ANALOG INPUTS Differential Input Full-Scale Voltage Range Matching Absolute AIN Voltage Limits Absolute AINCOM Voltage Limits B Grade Unit Test Conditions 5.4 105 16 13 16 See Tables in ADC Description ± 15 ±3 10 ± 0.75 ± 0.
PAGE 8
1 (AV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = AD7708 AD7718–SPECIFICATIONS 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T to T unless otherwise noted.
PAGE 9
AD7708/AD7718 TIMING CHARACTERISTICS1, 2 (AV DD = 2.7 V to 3.6 V or AVDD = 5 V ⴞ 5%; DVDD = 2.7 V to 3.6 V or DVDD = 5 V ⴞ 5%; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted. Parameter t1 t2 Read Operation t3 t4 t5 4 t5A4, 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments 32.
PAGE 10
AD7708/AD7718 ABSOLUTE MAXIMUM RATINGS* Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C SOIC Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 71.4°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 23°C/W TSSOP Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . .
PAGE 11
AD7708/AD7718 CS t11 t16 t14 SCLK t15 t12 t13 DIN MSB LSB Figure 2. Write Cycle Timing Diagram RDY t3 t10 CS t4 t8 t6 SCLK t5 t7 t6 t9 t5A DOUT MSB LSB Figure 3. Read Cycle Timing Diagram REV.
PAGE 12
AD7708/AD7718 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 AIN7 2 AIN8 3 4 5 6 AVDD AGND REFIN1(–) REFIN1(+) 7 AIN1 8 AIN2 9 AIN3 10 AIN4 11 AIN5 12 13 AINCOM REFIN2(+)/AIN9 14 REFIN2(–)/AIN10 15 AIN6 16 P2 17 18 AGND P1 19 RESET 20 SCLK Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudodifferential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN8.
PAGE 13
AD7708/AD7718 Pin No Mnemonic Function 21 CS 22 RDY 23 DOUT 24 DIN 25 26 27 28 DGND DVDD XTAL2 XTAL1 Chip Select Input. This is an active low logic input used to select the AD7708/AD7718. CS can be used to select the AD7708/AD7718 in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the AD7708/AD7718 to be operated in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device.
PAGE 14
AD7708/AD7718–Typical Performance Characteristics 26 8389600 AVDD = DVDD = 5V INPUT RANGE = ⴞ20mV 8389400 REFIN1(+)–REFIN1(–) = 2.5V UPDATE RATE = 19.79Hz CHOP = 0 NO MISSING CODES – Min 24 CODE READ 8389200 8389000 8388800 8388600 8388400 22 20 18 8388200 TA = 25ⴗC VREF = 2.5V RMS NOISE = 0.58␮V rms 8388000 0 100 200 300 400 500 600 READING NUMBER 700 16 0 900 1000 800 10 20 30 40 50 60 70 80 90 100 110 UPDATE RATE – Hz TPC 1.
PAGE 15
AD7708/AD7718 filter whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and decimated output data rate of the filter are programmable via the SF word loaded to the filter register. The complete signal chain is chopped resulting in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors.
PAGE 16
AD7708/AD7718 0 Table I. ADC Conversion and Settling Times for Various SF Words with CHOP = 0 Data Update Rate fADC (Hz) Settling Time tSETTLE (ms) 13 23 27 45 69 (Default) 91 182 255 105.3 59.36 50.56 30.3 19.79 15 7.5 5.35 19.04 33.69 39.55 65.9 101.07 133.1 266.6 373.54 –40 –60 ATTENUATION – dB SF Word –20 –80 –100 –120 –140 –160 –180 –200 0 The overall frequency response is the product of a sinc3 and a sinc response.
PAGE 17
0 0 –20 –20 –40 –40 ATTENUATION – dB ATTENUATION – dB AD7708/AD7718 –60 –80 –100 –80 –100 –120 –120 –140 –140 –160 0 10 20 30 40 50 60 70 80 90 –160 100 0 FREQUENCY – Hz 20 30 40 50 60 FREQUENCY – Hz 70 80 90 100 Figure 9. Filter Profile with SF = 68 Figure 7. Filter Profile with SF = 255 ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = 0) 0 –20 –40 –60 –80 –100 –120 –140 –160 0 10 20 30 40 50 60 FREQUENCY – Hz 70 80 90 100 SF = 69 OUTPUT DATA RATE = 19.
PAGE 18
AD7708/AD7718 Table II. Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Enabled (CHOP = 0); Output RMS Noise in ␮V SF Word Data Update Rate (Hz) ⴞ20 mV ⴞ40 mV ⴞ80 mV Input Range ⴞ160 mV ⴞ320 mV ⴞ640 mV ⴞ1.28 V ⴞ2.56 V 13 23 27 69 255 105.3 59.36 50.56 19.79 5.35 1.50 1.02 0.95 0.65 0.35 1.60 1.06 0.98 0.65 0.37 1.75 1.15 1.00 0.65 0.37 4.50 1.77 1.66 0.95 0.51 6.70 3.0 11.75 5.08 5.0 2.30 1.25 1.50 1.0 0.95 0.60 0.35 3.50 1.22 1.10 0.65 0.37 1.40 0.
PAGE 19
AD7708/AD7718 SIGNAL CHAIN OVERVIEW CHOP DISABLED (CHOP = 1) Table VI. ADC Conversion and Settling Times for Various SF Words with CHOP = 1 With CHOP =1 chopping is disabled. With chopping disabled the available output rates vary from 16.06 Hz (62.26 ms) to 1365.33 Hz (0.73 ms). The range of applicable SF words is from 3 to 255. When switching between channels with chop disabled, the channel throughput is increased by a factor of two over the case where chop is enabled.
PAGE 20
0 0 –20 –20 –40 –40 –60 –60 ATTENUATION – dB ATTENUATION – dB AD7708/AD7718 –80 –100 –120 –140 –80 –100 –120 –140 –160 –160 –180 –180 –200 –200 0 10 20 30 40 50 60 FREQUENCY – Hz 70 80 90 100 0 SF = 68 OUTPUT DATA RATE = 60.2Hz SETTLING TIME = 49.8ms INPUT BANDWIDTH = 15.5Hz 50Hz REJECTION = –43dB, 50Hzⴞ1Hz REJECTION = –40dB 60Hz REJECTION = –147dB, 60Hzⴞ1Hz REJECTION = –101dB 20 30 40 50 60 FREQUENCY – Hz 70 80 90 100 SF = 151 OUTPUT DATA RATE = 27.
PAGE 21
AD7708/AD7718 Table VII. Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Disabled (CHOP = 1); Output RMS Noise in ␮V SF Word Data Update Rate (Hz) ⴞ20 mV ⴞ40 mV ⴞ80 mV Input Range ⴞ160 mV ⴞ320 mV ⴞ640 mV ⴞ1.28 V ⴞ2.56 V 03 13 66 69 81 255 1365.33 315.08 62.06 59.38 50.57 16.06 29.02 2.49 0.852 0.971 0.872 0.468 58.33 2.37 0.9183 0.949 0.872 0.434 112.7 3.87 0.8788 0.922 0.806 0.485 361.72 12.61 1.29 1.32 1.34 0.688 616.89 16.65 1.99 2.03 2.18 1.18 1660 32.45 3.
PAGE 22
AD7708/AD7718 port. The filter register is a read/write register used to program the data update rate of the converter. The ADC Data register is a read only register that contains the result of a data conversion on the selected channel. The ADC offset registers are read/write registers that contain the offset calibration data. There are five offset registers, one for each of the fully differential input channels. When configured for pseudo-differential input mode the channels share offset registers.
PAGE 23
AD7708/AD7718 Table XI. Registers—Quick Reference Guide Register Name Type Size Power-On/Reset Default Value Communications Write Only 8 Bits Not Applicable CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN R/W 0(0) 0(0) A3(0) A2(0) A1(0) A0(0) Read Only 8 Bits Status Register 00 Hex MSB RDY Function All operations to other registers are initiated through the Communications Register.
PAGE 24
AD7708/AD7718 Table XI. Registers—Quick Reference Guide (continued) Power-On/Reset Register Name Type Size Default Value Function AD7718 Offset Register Read/Write 24 Bits 800 000 Hex Contains a 24-bit word which is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are five Offset Registers on the part and these are associated with input channels as outlined in the ADCCON register.
PAGE 25
AD7708/AD7718 Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation, and on which register this operation takes place.
PAGE 26
AD7708/AD7718 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex) The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communications Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream.
PAGE 27
AD7708/AD7718 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00Hex) The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7708/AD7718. Table XV outlines the bit designations for the Mode Register. MR7 through MR0 indicate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream.
PAGE 28
AD7708/AD7718 Operating Characteristics when Addressing the Mode and Control Registers 1. Any change to the MD bits will immediately reset the ADCs. A write to the MD2–MD0 bits with no change is also treated as a reset. 2. Once the MODE has been written with a calibration mode, the RDY bit (STATUS) is immediately reset and the calibration commences.
PAGE 29
AD7708/AD7718 Table XVI. ADC Control Register (ADCCON) Bit Designations (continued) AD0C2 AD0C1 AD0C0 RN2 RN1 RN0 ADC Range Bits Written by the user to select the ADC input range as follows RN2 RN1 RN0 Selected ADC Input Range (VREF = 2.5 V) 0 0 0 ± 20 mV 0 0 1 ± 40 mV 0 1 0 ± 80 mV 0 1 1 ± 160 mV 1 0 0 ± 320 mV 1 0 1 ± 640 mV 1 1 0 ± 1.28 V 1 1 1 ± 2.
PAGE 30
AD7708/AD7718 I/O Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On-Reset = 00Hex) The IOCON Register is an 8-bit register from which data can be read or to which data can be written. This register is used to control and configure the I/O port. Table XIX outlines the bit designations for this register. IOCON7 through IOCON0 indicate the bit location, IOCON denoting the bits are in the I/O Control Register. IOCON7 denotes the first bit of the data stream.
PAGE 31
AD7708/AD7718 Bipolar Mode With an analog input voltage of (–1.024 VREF/GAIN), the output code is 0000 Hex using the AD7708 and 000000H using the AD7718. With an analog input voltage of 0 V, the output code is 8000Hex for the AD7708 and 800000Hex for the AD7718. With an analog input voltage of (+1.024 VREF/GAIN), the output code is FFFF Hex for the AD7708 and FFFFFF Hex for the AD7718.
PAGE 32
AD7708/AD7718 Configuring the AD7708/AD7718 All user-accessible registers on the AD7708 and AD7718 are accessed via the serial interface. Communication with any of these registers is initiated by first writing to the Communications Register. Figures 16, 17, and 18 show flow diagrams for initializing the ADC, a sequence for calibrating the ADC channels, and a routine that cycles through and reads all channels. Figure 16 shows a flowchart detailing necessary programming steps required to initialize the ADC.
PAGE 33
AD7708/AD7718 1. Write to the ADCCON register to select the channel to be calibrated, its input range, and operation in unipolar or bipolar mode. 2. Write to the mode register selecting chop or nonchop mode of operation, select the reference, buffered/unbuffered operation on the AINCOM, and select zero-scale offset calibration.
PAGE 34
AD7708/AD7718 DIGITAL INTERFACE As previously outlined, the AD7708/AD7718’s programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register.
PAGE 35
AD7708/AD7718 AD7708/AD7718 to 68HC11 Interface AD7708/AD7718-to-8051 Interface Figure 19 shows an interface between the AD7708/AD7718 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7708/AD7718 hardwired low. In this scheme, the RDY bit of the Status Register is monitored to determine when the Data Register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the RDY output line from the AD7708/AD7718.
PAGE 36
AD7708/AD7718 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface BASIC CONFIGURATION Figure 21 shows an interface between the AD7708/AD7718 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the RDY bit of the Status Register is again monitored to determine when the Data Register is updated. The alternative scheme is to use an interrupt-driven system, in which case the RDY output is connected to the IRQ2 input of the ADSP-2103/ ADSP-2105.
PAGE 37
AD7708/AD7718 Analog Input Channels The input multiplexer on AD7708/AD7718 can be configured as either an 8- or 10-input channel device. This configuration is selected using the CHCON bit in the MODE register. With CHCON = 0 (Figure 23), the user has eight input channels; these can be configured as eight pseudo-differential input channels with respect to AINCOM or four fully-differential input channels.
PAGE 38
AD7708/AD7718 19.372 Nonchop Mode of Operation (CHOP = 1) Chopping is enabled and disabled using the CHOP bit in the mode register. Chopping is disabled by loading a 1 to the chop bit in the mode register. With chopping disabled the available output rates vary from 16.06 Hz (62.26 ms) to 1365.33 Hz (0.73 ms). The range of applicable SF words is from 3 to 255.
PAGE 39
AD7708/AD7718 The output code for any analog input voltage on the AD7708 can be represented as follows: Code = (AIN × GAIN × 216)/(1.024 × VREF) where AIN is the analog input voltage, GAIN is the PGA gain, i.e., 1 on the 2.5 V range and 128 on the 20 mV range. When an ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . .
PAGE 40
AD7708/AD7718 Calibration The AD7708/AD7718 provides four calibration modes that can be programmed via the mode bits in the mode register. One of the major benefits of the AD7708/AD7718 is that it is factorycalibrated with chopping enabled as part of the final test process with the generated coefficients stored within the ADC. At poweron, the factory gain calibration coefficients are automatically loaded to the gain calibration registers on the AD7708/AD7718.
PAGE 41
AD7708/AD7718 The buffer on the negative analog input can be bypassed allowing the AD7708/AD7718 be operated as eight or ten single-ended input channels. The PGA allows the user to connect transducers directly to the input of the AD7708/AD7718. The programmable gain front end on the AD7708/AD7718 allows the part to handle unipolar analog input ranges from 0 mV to +20 mV to 0 V to +2.5 V and bipolar inputs of ±20 mV to ± 2.5 V.
PAGE 42
AD7708/AD7718 Converting Single-Ended Inputs The AD7708/AD7718 generally operates in buffered mode. This places a restriction of AGND + 100 mV to AVDD – 100 mV on the absolute and common-mode voltages that can be applied to any input on the AD7708/AD7718. Some applications may require the measurement of analog inputs with respect to AGND. To enable the AD7708/AD7718 to be used in these single-ended applications, the buffer on the AINCOM can be bypassed.
PAGE 43
AD7708/AD7718 Optimizing Throughput while Maximizing 50 Hz and 60 Hz Rejection in a Multiplexed Data Acquisition System The AD7708/AD7718 can be optimized for one of two modes of operation. Operating the AD7708/AD7718 with chopping enabled (CHOP = 0) optimizes the AD7708/AD7718 for analog performance over channel throughput. Output data rates vary from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).
PAGE 44
AD7708/AD7718 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C01831–1–7/01(0) 28-Lead Plastic SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 1 0.4193 (10.65) 0.3937 (10.00) 14 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0291 (0.74) ⴛ 45ⴗ 0.0098 (0.25) 8ⴗ 0ⴗ 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead Plastic TSSOP (RU-28) 0.386 (9.80) 0.378 (9.