Datasheet

AD7707
Rev. B | Page 6 of 52
Parameter B Version
1
Unit Conditions/Comments
MCLK IN Only DV
DD
= 5 V nominal
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 3.5 V min
MCLK IN Only DV
DD
= 3 V nominal
V
INL
, Input Low Voltage 0.4 V max
V
INH
, Input High Voltage 2.5 V min
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 800 μA except for MCLK OUT
13
; DV
DD
= 5 V
0.4 V max
I
SINK
= 100 μA except for MCLK OUT
13
; DV
DD
= 3 V
V
OH
, Output High Voltage 4 V min
I
SOURCE
= 200 μA except for MCLK OUT
13
; DV
DD
= 5 V
DV
DD
− 0.6 V min
I
SOURCE
= 100 μA except for MCLK OUT
13
; DV
DD
= 3 V
Floating State Leakage Current ±10 μA max
Floating State Output Capacitance
14
9 pF typ
Data Output Coding Binary Unipolar mode
Offset binary Bipolar mode
SYSTEM CALIBRATION
Low Level Input Channels (AIN1 and AIN2)
Positive Full-Scale Calibration Limit
15
(1.05 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
Negative Full-Scale Calibration Limit
15
−(1.05 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
Offset Calibration Limit
16
−(1.05 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
Input Span
16
(0.8 × V
REF
)/gain V min Gain is the selected PGA gain (1 to 128)
(2.1 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
High Level Input Channels (AIN3)
Positive Full-Scale Calibration Limit
15
(8.4 × V
REF
)/gain V max Gain is the selected PGA gain (1 to 128)
Negative Full-Scale Calibration Limit
15
−(8.4 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
Offset Calibration Limit
16
−(8.4 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
Input Span
16
(6.4 × V
REF
)/gain V min Gain is the selected PGA gain (1 to 128)
(16.8 ×
V
REF
)/gain
V max Gain is the selected PGA gain (1 to 128)
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage 2.7 to 3.3 or
4.75 to 5.25 V min to V max For specified performance
DV
DD
Voltage 2.7 to 5.25 V min to V max For specified performance
Power Supply Currents
AV
DD
Current AV
DD
= 3 V or 5 V; gain = 1 to 4
0.27 mA max Typically 0.22 mA; BUF = 0; f
CLK IN
= 1 MHz or 2.4576 MHz
0.6 mA max Typically 0.45 mA; BUF = 1; f
CLK IN
= 1 MHz or 2.4576 MHz
AV
DD
= 3 V or 5 V; gain = 8 to 128
0.5 mA max Typically 0.38 mA; BUF = 0; f
CLK IN
= 2.4576 MHz
1.1 mA max Typically 0.81 mA; BUF = 1; f
CLK IN
= 2.4576 MHz
POWER REQUIREMENTS (Continued)
DV
DD
Current
17
Digital inputs = 0 V or DV
DD
; external MCLK IN
0.080 mA max Typically 0.06 mA; DV
DD
= 3 V; f
CLK IN
= 1 MHz
0.15 mA max Typically 0.13 mA; DV
DD
= 5 V; f
CLK IN
= 1 MHz
0.18 mA max Typically 0.15 mA; DV
DD
= 3 V; f
CLK IN
= 2.4576 MHz
0.35 mA max Typically 0.3 mA; DV
DD
= 5 V; f
CLK IN
= 2.4576 MHz
Power Supply Rejection
18, 19
dB typ