Datasheet

AD7705/AD7706
Rev. C | Page 8 of 44
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.25 V; GND = 0 V; f
CLKIN
= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = V
DD
, unless otherwise noted.
Table 2. Timing Characteristics
1, 2
Parameter
Limit at T
MIN
, T
MAX
(B Version) Unit Conditions/Comments
f
CLKIN
3, 4
400 kHz min Master clock frequency (crystal oscillator or externally supplied)
2.5 MHz max For specified performance
t
CLKIN LO
0.4 × t
CLKIN
ns min Master clock input low time, t
CLKIN
= 1/f
CLKIN
t
CLKIN HI
0.4 × t
CLKIN
ns min Master clock input high time
t
1
500 × t
CLKIN
ns nom
DRDY
high time
t
2
100 ns min
RESET
pulse width
Read Operation
t
3
0 ns min
DRDY
to CS setup time
t
4
120 ns min
CS
falling edge to SCLK rising edge setup time
t
5
5
0 ns min SCLK falling edge to data valid delay
80 ns max V
DD
= 5 V
100 ns max V
DD
= 3.0 V
t
6
100 ns min SCLK high pulse width
t
7
100 ns min SCLK low pulse width
t
8
0 ns min
CS
rising edge to SCLK rising edge hold time
t
9
6
10 ns min Bus relinquish time after SCLK rising edge
60 ns max V
DD
= 5 V
100 ns max V
DD
= 3.0 V
t
10
100 ns max
SCLK falling edge to DRDY
high
7
Write Operation
t
11
120 ns min
CS
falling edge to SCLK rising edge setup time
t
12
30 ns min Data valid to SCLK rising edge setup time
t
13
20 ns min Data valid to SCLK rising edge hold time
t
14
100 ns min SCLK high pulse width
t
15
100 ns min SCLK low pulse width
t
16
0 ns min
CS
rising edge to SCLK rising edge hold time
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 19 and Figure 20.
3
The f
CLKIN
duty cycle range is 45% to 55%. f
CLKIN
must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw
higher current than specified, and possibly become uncalibrated.
4
The AD7705/AD7706 are production tested with f
CLKIN
at 2.4576 MHz (1 MHz for some I
DD
tests). They are guaranteed by characterization to operate at 400 kHz.
5
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY
returns high upon completion of the first read from the device after an output update. The same data can be reread while
DRDY
is high, but care should be
taken that subsequent reads do not occur close to the next output update.
TO OUTPUT
PIN
50pF
I
SINK
(800μA AT V
DD
= 5V
100μA AT V
DD
= 3V)
1.6V
I
SOURCE
(200μA AT V
DD
= 5V
100mA AT V
DD
= 3V)
01166-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time