Datasheet

REV. E–4–
AD7703
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments
f
CLKIN
3, 4
200 200 kHz min Master Clock Frequency: Internal Gate Oscillator
55MHz max Typically 4.096 MHz
200 200 kHz min Master Clock Frequency: Externally Supplied
55MHz max
t
r
5
50 50 ns max Digital Output Rise Time. Typically 20 ns.
t
f
5
50 50 ns max Digital Output Fall Time. Typically 20 ns.
t
1
00ns min SC1, SC2 to CAL High Setup Time
t
2
50 50 ns min SC1, SC2 Hold Time after CAL Goes High
t
3
6
1000 1000 ns min SLEEP High to CLKIN High Setup Time
SSC MODE
t
4
7
3/f
CLKIN
3/f
CLKIN
ns max Data Access Time (CS Low to Data Valid)
t
5
100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)
t
6
250 250 ns min MSB Data Setup Time. Typically 380 ns.
7
300 300 ns max SCLK High Pulsewidth. Typically 240 ns.
t
8
790 790 ns max SCLK Low Pulsewidth. Typically 730 ns.
t
9
8
l/f
CLKIN
+ 200 l/f
CLKIN
+ 200 ns max SCLK Rising Edge to Hi-Z Delay (l/f
CLKIN
+ 100 ns typ)
t
10
8, 9
4/f
CLKIN
+ 200 4/f
CLKIN
+ 200 ns max CS High to Hi-Z Delay
SEC MODE
f
SCLK
55MHz max Serial Clock Input Frequency
t
11
35 35 ns min SCLK Input High Pulsewidth
t
12
160 160 ns min SCLK Low Pulsewidth
t
13
7, 10
160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.
t
14
11
150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
t
15
8
250 250 ns max CS High to Hi-Z Delay
t
16
8
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4
The AD7703 is production tested with f
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7
t
4
and t
13
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t
9
, t
10
, t
15
, and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V ⴞ 10%; AV
SS
= DV
SS
= –5 V ⴞ 10%; AGND = DGND = O V;
f
CLKIN
= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
DD
; unless otherwise noted.)
C
L
100pF
TO
OUTPUT
PIN
I
OH
200␮A
2.1V
+
I
OL
1.6mA
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
CAL
SC1, SC2
SC1, SC2 VALID
t
1
t
2
Figure 2. Calibration Control Timing
CLKIN
SLEEP
t
3
Figure 3. Sleep Mode Timing