Datasheet

Data Sheet AD7699
Rev. | Page 5 of 28
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, V
REF
= 4.096 to VDD, VIO = 1.8 V to VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
1.6 µs
Acquisition Time t
ACQ
400 ns
Time Between Conversions t
CYC
2 µs
CNV Pulse Width t
CNVH
10 ns
Data Write/Read During Conversion t
DATA
1.2 µs
SCK Period t
SCK
t
DSDO
+ 2 ns
SCK Low Time t
SCKL
11 ns
SCK High Time t
SCKH
11 ns
SCK Falling Edge to Data Remains Valid t
HSDO
4 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 4.5 V 16 ns
VIO Above 3 V 17 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 21 ns
VIO Above 1.8 V 28 ns
CNV Low to SDO D15 MSB Valid t
EN
VIO Above 4.5 V 15 ns
VIO Above 3 V 17 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
VIO Above 1.8 V 25 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
DIS
32 ns
CNV Low to SCK Rising Edge t
CLSCK
10 ns
DIN Valid Setup Time from SCK Falling Edge t
SDIN
5 ns
DIN Valid Hold Time from SCK Falling Edge t
HDIN
5 ns
1
See and for load conditions. Figure 2 Figure 3
I
OL
500µA
500µA
I
OH
1.4V
T
OSDO
C
L
50pF
07354-002
Figure 2. Load Circuit for Digital Interface Timing
3
0% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
07354-003
Figure 3. Voltage Levels for Timing
B