Datasheet

AD7693
Rev. A | Page 19 of 24
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
th
SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD7693 can
be read.
DATA IN
CLK
CS1
CONVERT
CS2
CNV
SCK
SDOSDI
CNV
SCK
SDOSDI
AD7693AD7693
0
6394-037
DIGITAL HOST
Figure 38.
CS
Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D15 D14 D13 D1 D0
t
DIS
SCK
123 303132
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
14 15
t
SCK
t
SCKL
t
SCKH
D0 D16 D15
17 1816
SDI(CS2)
0
6394-038
Figure 39.
CS
Mode, 4-Wire Without Busy Indicator Serial Interface Timing