Datasheet

AD7690
Rev. B | Page 16 of 24
POWER SUPPLY
The AD7690 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows a direct
interface with any logic between 1.8 V and V
DD
. To reduce the
number of supplies needed, the VIO and VDD pins can be tied
together. The AD7690 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in Figure 31.
95
65
1 10000
FREQUENCY (kHz)
PSRR (dB)
05792-035
90
85
80
75
70
10 100 1000
Figure 31. PSRR vs. Frequency
The AD7690 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rates (even of a few hertz) and low battery-powered applications.
1000
10
0.1
0.001
10 1M
SAMPLING RATE (SPS)
OPERATING CURRENT (µA)
05792-045
100 1k 100k10k
VDD = 5V
VIO
0.01
1
100
10000
Figure 32. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7690, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by
• The system power supply directly.
• A reference voltage with enough current output capability,
such as the ADR43x.
• A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
AD8031
AD7690
VIOREF VDD
10µF 1µF
10Ω
10kΩ
5V
5V
5V
1µF
1
05792-046
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 33. Example of Application Circuit
DIGITAL INTERFACE
Though the AD7690 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in
CS
mode, the AD7690 is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. In this mode, the AD7690 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7690 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
CS
mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
In either mode, the AD7690 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled
• In
CS
mode if CNV or SDI is low when the ADC conversion
ends (see and ). Figure 37 Figure 41
• In chain mode if SCK is high during the CNV rising edge
(see Figure 45).