Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External MSOP 10

16-Bit, 500 kSPS PulSAR

ADC in MSOP/QFN

AD7686

Rev. B

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FEATURES

16-bit resolution with no missing codes

Throughput: 500 kSPS

INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR)

SINAD: 92.5 dB @ 20 kHz

THD: −110 dB @ 20 kHz

Pseudo differential analog input range

0 V to V

REF

with V

REF

up to VDD

No pipeline delay

Single-supply 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface

Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Daisy-chain multiple ADCs and busy indicator

Power dissipation

3.75 μW @ 5 V/100 SPS

3.75 mW @ 5 V/100 kSPS

Standby current: 1 nA

10-lead MSOP (MSOP-8 size) and

3 mm × 3 mm, 10-lead QFN (LFCSP) (SOT-23 size)

Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs

APPLICATIONS

Battery-powered equipment

Data acquisitions

Instrumentation

Medical instruments

Process controls

CODE

INL (LSB)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

0 16384 32768 49152 65535

02969-007

POSITIVE INL = +0.52LSB

NEGATIVE INL = –0.38LSB

Figure 1. Integral Nonlinearity vs. Code

FUNCTIONAL BLOCK DIAGRAM

AD7686

REF

GND

VDD

IN+

IN–

VIO

SDI

SCK

SDO

CNV

1.8V TO VDD

3- OR 4-WIRE INTERFACE

(SPI, DAISY CHAIN, CS)

0.5

TO 5V 5

0TO VREF

02969-002

Figure 2.

Table 1. MSOP, QFN (LFCSP)/SOT-23

14-/16-/18-Bit PulSAR ADC

Type

100

kSPS

250

kSPS

400 kSPS

500 kSPS

1000

kSPS

ADC

Driver

18-Bit True AD7691 AD7690 AD7982 ADA4941

Differential AD7982 ADA4841

16-Bit True AD7684 AD7687 AD7688 ADA4941

Differential AD7693 ADA4841

16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841

Differential AD7683 AD7694

14-Bit Pseudo

Differential

AD7940 AD7942 AD7946 ADA4841

GENERAL DESCRIPTION

The AD7686 is a 16-bit, charge redistribution, successive

approximation, analog-to-digital converter (ADC) that operates

from a single 5 V power supply, VDD. It contains a low power,

high speed, 16-bit sampling ADC with no missing codes, an

internal conversion clock, and a versatile serial interface port.

The part also contains a low noise, wide bandwidth, short

aperture delay track-and-hold circuit. On the CNV rising edge,

the AD7686 samples an analog input IN+ between 0 V to REF

with respect to a ground sense IN−. The reference voltage, REF,

is applied externally and can be set up to the supply voltage.

Power dissipation scales linearly with throughput.

The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single,

3-wire bus or provides an optional busy indicator. This device is

compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate

supply VIO.

The AD7686 is housed in a 10-lead MSOP or a 10-lead QFN

(LFCSP) with operation specified from −40°C to +85°C.

Summary of content (28 pages)

PAGE 1
6-Bit, 500 kSPS PulSAR ADC in MSOP/QFN AD7686 FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Battery-powered equipment Data acquisitions Instrumentation Medical instruments Process controls IN– AD7686 1.8V TO VDD SCK 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) SDO GND CNV Figure 2. Table 1.
PAGE 2
AD7686 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 15 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 15 Functional Block Diagram ..............................................................
PAGE 3
AD7686 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2.
PAGE 4
AD7686 VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation ISINK = +500 μA ISOURCE = −500 μA TEMPERATURE RANGE 3 Specified Performance Min Typ 0.5 Max Unit VDD + 0.
PAGE 5
AD7686 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width ( CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.
PAGE 6
AD7686 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+ 1 , IN−1 REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature 1 Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.
PAGE 7
AD7686 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 VIO VDD 2 AD7686 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV VDD 2 IN+ 3 IN– 4 GND 5 IN– 4 GND 5 Figure 5. 10-Lead MSOP Pin Configuration 10 VIO AD7686 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV 02969-006 10 02969-005 REF 1 Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 8
AD7686 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 25).
PAGE 9
AD7686 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –1.0 –1.0 –1.5 –1.5 02969-007 –0.5 –2.0 0 16384 32768 CODE 49152 POSITIVE DNL = +0.35LSB NEGATIVE DNL = –0.36LSB 1.5 DNL (LSB) INL (LSB) 2.0 POSITIVE INL = +0.52LSB NEGATIVE INL = –0.38LSB –2.0 65535 02969-010 2.0 0 Figure 7. Integral Nonlinearity vs. Code 16384 32768 CODE 49152 65535 Figure 10. Differential Nonlinearity vs.
PAGE 10
AD7686 100 17.0 –90 –95 16.0 95 –100 THD 70 2.3 2.7 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 13.0 5.5 5.1 SFDR –110 –115 –120 14.0 85 –105 –125 –130 2.3 Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 02969-016 ENOB THD, SFDR (dB) 15.0 90 ENOB (Bits) SINAD 02969-013 SNR, SINAD (dB) SNR 2.7 3.1 3.5 3.9 4.3 4.
PAGE 11
AD7686 1000 4 fS = 100kSPS OFFSET, GAIN ERROR (LSB) 500 250 VIO 0 4.50 4.75 5.00 SUPPLY (V) 5.25 2 OFFSET ERROR 1 –0 GAIN ERROR –1 –2 –3 –4 –55 5.50 Figure 19. Operating Currents vs. Supply –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 25 20 750 TDSDO DELAY (ns) 500 250 15 VDD = 5V, 85°C 10 VDD = 5V, 25°C 5 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 02969-020 VDD + VIO 105 125 Figure 20. Power-Down Currents vs.
PAGE 12
AD7686 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF LSB 32,768C 16,384C 4C 2C C SW+ C BUSY COMP GND 32,768C 16,384C 4C 2C C MSB CONTROL LOGIC OUTPUT CODE C LSB SW– 02969-024 CNV IN– Figure 24. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7686 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7686 is a successive approximation ADC based on a charge redistribution DAC.
PAGE 13
AD7686 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 111...111 111...110 111...101 Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V Digital Output Code Hexadecimal FFFF 1 8001 8000 7FFF 0001 0000 2 TYPICAL CONNECTION DIAGRAM Figure 26 shows an example of the recommended connection diagram for the AD7686 when multiple supplies are available. 000...010 000...001 000...
PAGE 14
AD7686 Figure 27 shows an equivalent circuit of the input structure of the AD7686. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes these diodes to begin to forward-bias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum.
PAGE 15
AD7686 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Although the AD7686 is easy to drive, the driver amplifier should meet the following requirements: The AD7686 voltage reference input, REF, has a dynamic input impedance and should, therefore, be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section.
PAGE 16
AD7686 The AD7686 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 31. This makes the part ideal for low sampling rates (even a few Hz) and low batterypowered applications. 10000 OPERATING CURRENTS (µA) 1000 VDD = 5V 100 10 VIO 1 10 100 1000 10000 SAMPLING RATE (SPS) 100000 02969-032 0.01 1000000 Figure 31. Operating Currents vs.
PAGE 17
AD7686 The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when CNV goes high, whichever occurs first, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is most often used when a single AD7686 is connected to an SPI-compatible digital host.
PAGE 18
AD7686 Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high, whichever occurs first, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is generally used when a single AD7686 is connected to an SPI-compatible digital host having an interrupt input.
PAGE 19
AD7686 avoid the generation of the busy signal indicator. When the conversion is complete, the AD7686 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges.
PAGE 20
AD7686 With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7686 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time.
PAGE 21
AD7686 When the conversion is complete, the MSB is output onto SDO, and the AD7686 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges.
PAGE 22
AD7686 This mode can be used to daisy-chain multiple AD7686s on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7686s is shown in Figure 43, and the corresponding timing is given in Figure 44.
PAGE 23
AD7686 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7686 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7686, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because doing so couples noise onto the die, unless a ground plane under the AD7686 is used as a shield.
PAGE 24
AD7686 This skew is the channel-to-channel matching propagation delay of the digital isolator (tPSKCD). This allows running the serial interface at the maximum speed of the digital isolator (45 Mbps for the ADuM1402C), which would have been otherwise limited by the cascade of the propagation delays of the digital isolator. For instance, four AD7686 devices running at 330 kSPS can be chained together.
PAGE 25
AD7686 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 6 1 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 0.80 0.60 0.40 8° 0° COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC SQ PIN 1 INDICATOR 1 10 1.50 BSC SQ 0.50 BSC (BOT TOM VIEW) 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.30 0.23 0.18 2.48 2.
PAGE 26
AD7686 ORDERING GUIDE Model AD7686BCPZRL 1 AD7686BCPZRL71 AD7686BRM AD7686BRMRL7 AD7686BRMZ1 AD7686BRMZRL71 AD7686CCPZRL1 AD7686CCPZRL71 AD7686CRM AD7686CRMRL7 AD7686CRMZ1 AD7686CRMZRL71 EVAL-AD7686CB 2 EVAL-AD7686CBZ1, 2 EVAL-CONTROL BRD2 3 EVAL-CONTROL BRD33 Integral Nonlinearity ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max ±2 LSB max Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –4
PAGE 27
AD7686 NOTES Rev.