Datasheet

AD7686
Rev. B | Page 23 of 28
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7686
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7686, with all its analog signals on the left side
and all its digital signals on the right side, eases this task.
Avoid running digital lines under the device because doing so
couples noise onto the die, unless a ground plane under the
AD7686 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the devices.
The AD7686 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the AD7686 power supplies VDD and VIO should be
decoupled with ceramic capacitors (typically 100 nF) placed
close to the AD7686 and connected using short and wide traces.
This provides low impedance paths and reduces the effect of
glitches on the power supply lines. Examples of layouts that
follow these rules are shown in
Figure 45 and Figure 46.
EVALUATING PERFORMANCE
Other recommended layouts for the AD7686 are outlined in
the documentation of the evaluation board (
EVAL-AD7686CB).
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the universal evaluation
control board (
EVAL-CONTROL BRD3).
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Figure 45. Example of Layout of the AD7686 (Top Layer)
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Figure 46. Example of Layout of the AD7686 (Bottom Layer)