Datasheet

AD7686
Rev. B | Page 17 of 28
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is most often used when a single AD7686 is
connected to an SPI-compatible digital host. The connection
diagram is shown in
Figure 33, and the corresponding timing is
provided in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the
CS
mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers. However, CNV must be returned
high before the minimum conversion time and held high until
the maximum conversion time to avoid generating the busy
signal indicator. When the conversion is complete, the AD7686
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided it has an
acceptable hold time. After the 16th SCK falling edge, or when
CNV goes high, whichever occurs first, SDO returns to high
impedance.
CNV
SCK
SDOSDI
DATA IN
CLK
CONVERT
V
IO
DIGITAL HOST
AD7686
02969-034
Figure 33.
CS
Mode 3-Wire, No Busy Indicator
Connection Diagram (SDI High)
SDO
D15 D14 D13 D1 D0
t
DIS
SCK
123 141516
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
02969-035
Figure 34.
CS
Mode 3-Wire, No Busy Indicator Serial Interface Timing (SDI High)