Datasheet

AD7685
Rev. C | Page 22 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7685s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7685s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the
chain mode. In this mode, CNV is held high during the
conversion phase and the subsequent data readback. When the
conversion is complete, the MSB is output onto SDO and the
AD7685 enters the acquisition phase and powers down. The
remaining data bits stored in the internal shift register are then
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 16 × N clocks are required to readback the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate and, consequently,
more AD7685s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time. For instance, with a 5 ns
digital host setup time and 3 V interface, up to eight AD7685s
running at a conversion rate of 220 kSPS can be daisy-chained
on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
02968-040
CNV
SCK
SDOSDI
AD7685
B
CNV
SCK
SDOSDI
AD7685
A
Figure 42. Chain Mode Connection Diagram
SDO
A
= SDI
B
D
A
15 D
A
14 D
A
13
SCK
1 2 3 303132
t
SSDISCK
t
HSDISCK
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
14 15
t
SCK
t
SCKL
t
SCKH
D
A
0
17 1816
SDI
A
= 0
SDO
B
D
B
15 D
B
14 D
B
13 D
A
1D
B
1D
B
0D
A
15 D
A
14
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
02968-041
Figure 43. Chain Mode Serial Interface Timing