Datasheet

AD7685
Rev. C | Page 19 of 28
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the
CS
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7685 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
02968-034
47kΩ
CNV
SCK
SDOSDI
V
IO
AD7685
Figure 36.
CS
Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDO
D15 D14 D1 D0
t
DIS
SCK
1 2 3 15 16 17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
SDI = 1
0
2968-035
Figure 37.
CS
Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)