Datasheet

AD7683
Rev. A | Page 5 of 16
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate t
CYC
100 kHz
CS Falling to DCLOCK Low
t
CSD
0 μs
CS Falling to DCLOCK Rising
t
SUCS
20 ns
DCLOCK Falling to Data Remains Valid t
HDO
5 16 ns
CS Rising Edge to D
OUT
High Impedance
t
DIS
14 100 ns
DCLOCK Falling to Data Valid t
EN
16 50 ns
Acquisition Time t
ACQ
400 ns
D
OUT
Fall Time t
F
11 25 ns
D
OUT
Rise Time t
R
11 25 ns
Timing and Circuit Diagrams
04301-002
D
OUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
HIGH-Z
0
HIGH-Z
t
ACQ
t
DIS
0
145
t
HDO
t
EN
t
CSD
t
SUCS
t
CYC
NOTES
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
04301-003
500µA I
OL
500µA I
OH
1.4V
T
O D
OUT
C
L
100pF
Figure 3. Load Circuit for Digital Interface Timing
0.8V
2V
2V
0.8V0.8V
2V
t
EN
t
EN
04301-004
Figure 4. Voltage Reference Levels for Timing
04301-006
D
OUT
90%
10%
t
R
t
F
Figure 5. D
OUT
Rise and Fall Timing