Datasheet

AD7680
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS
1
Table 4. V
DD
= 2.5 V to 5.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Limit at T
MIN
, T
MAX
Parameter 3 V 5 V Unit Description
f
SCLK
2
250 250 kHz min
2.5 2.5 MHz max
t
CONVERT
20 × t
SCLK
20 × t
SCLK
min
t
QUIET
100 100 ns min Minimum quiet time required between bus relinquish and start of next conversion
t
1
10 10 ns min
Minimum
CS
pulse width
t
2
10 10 ns min
CS
to SCLK setup time
t
3
3
48 35 ns max
Delay from
CS
until SDATA three-state disabled
t
4
3
120 80 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK high pulse width
t
7
10 10 ns min SCLK to data valid hold time
t
8
4
45 35 ns max SCLK falling edge to SDATA high impedance
t
POWER-UP
5
1 1 μs typ Power up time from full power-down
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power vs. Throughput Rate section.
03643-0-002
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specification