Datasheet

AD7679
Rev. A | Page 21 of 28
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
MASTER SERIAL INTERFACE
Internal Clock
The AD7679 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held low. The
AD7679 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. and show
the detailed timing diagrams of these two modes.
Figure 38 Figure 39
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
Usually, because the AD7679 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
123 161718
D17 D16 D2 D1 D0X
EXT/INT = 0
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
03085-0-040
Figure 38. Master Serial Data Timing for Reading (Read after Convert)