Datasheet

REV. A
AD7677
–4–
TIMING SPECIFICATIONS
Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t
1
5ns
Time Between Conversions t
2
1/1.25/1.5 Note 1 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes Except in t
4
0.75/1/1.25 µs
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time t
8
250 ns
RESET Pulsewidth t
9
10 ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay (Read During Convert) t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
t
18
3ns
Internal SCLK Period
3
t
19
25 40 ns
Internal SCLK HIGH
3
t
20
12 ns
Internal SCLK LOW
3
t
21
7ns
SDOUT Valid Setup Time
3
t
22
4ns
SDOUT Valid Hold Time
3
t
23
2ns
SCLK Last Edge to SYNC Delay
3
t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read After Convert
3
t
28
See Table I
CNVST LOW to SYNC Asserted Delay t
29
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 19 and 20 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
318ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)