Datasheet

REV. B
–3–
AD7676
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t
1
5ns
Time between Conversions t
2
2 µs
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes except in Master Serial Read t
4
1.25 µs
Convert Mode
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.25 µs
Acquisition Time t
8
750 ns
RESET Pulsewidth t
9
10 ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
1.25 ns
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
Refer to Figures 16 and 17 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
525 ns
SYNC Asserted to SCLK First Edge Delay
2
t
18
3ns
Internal SCLK Period
2
t
19
25 40 ns
Internal SCLK HIGH
2
t
20
12 ns
Internal SCLK LOW
2
t
21
7ns
SDOUT Valid Setup Time
2
t
22
4ns
SDOUT Valid Hold Time
2
t
23
2ns
SCLK Last Edge to SYNC Delay
2
t
24
3ns
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
2
t
28
See Table I
CNVST LOW to SYNC Asserted Delay t
29
1.25 µs
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 18 and 19 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
318ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert Mode, see Table II.
Specifications subject to change without notice.
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)