Datasheet

AD7674
Rev. A | Page 6 of 28
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
Symbol
0 0 1 1
Unit
DIVSCLK[0] 0 1 0 1
SYNC to SCLK First Edge Delay Minimum t
18
3 17 17 17 ns
Internal SCLK Period Minimum t
19
25 60 120 240 ns
Internal SCLK Period Maximum t
19
40 80 160 320 ns
Internal SCLK HIGH Minimum t
20
12 22 50 100 ns
Internal SCLK LOW Minimum t
21
7 21 49 99 ns
SDOUT Valid Setup Time Minimum t
22
4 18 18 18 ns
SDOUT Valid Hold Time Minimum t
23
2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t
24
3 60 140 300 ns
Busy High Width Maximum (Warp) t
28
1.75 2.5 4 7 μs
Busy High Width Maximum (Normal) t
28
2 2.75 4.25 7.25 μs
Busy High Width Maximum (Impulse) t
28
2.25 3 4.5 7.5 μs