Datasheet

AD7674
Rev. A | Page 22 of 28
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
123 161718
D17 D16 D2 D1 D0X
EXT/INT = 0
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
03083-0-040
Figure 40. Master Serial Data Timing for Reading (Read after Convert)
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SCLK
S
DOUT
CS, RD
CNVST
t
3
t
1
t
17
t
14
t
15
t
19
t
20
t
21
t
16
t
22
t
23
t
24
t
27
t
26
t
25
t
18
EXT/INT = 0
03083-0-046
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SLAVE SERIAL INTERFACE
External Clock
The AD7674 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by
CS
. When
CS
and
RD
are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 42 and Figure 43 show the detailed timing
diagrams of these methods.
While the AD7674 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or