Datasheet
REV.
AD7665
–4–
TIMING SPECIFICATIONS
(continued)
Parameter
Symbol Min Typ Max Unit
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay (Read during Convert) t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
t
18
4ns
Internal SCLK Period
3
t
19
25 40 ns
Internal SCLK HIGH
3
t
20
15 ns
Internal SCLK LOW
3
t
21
9.5 ns
SDOUT Valid Setup Time
3
t
22
4.5 ns
SDOUT Valid Hold Time
3
t
23
2ns
SCLK Last Edge to SYNC Delay
3
t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
3
t
28
See Table II µs
CNVST LOW to SYNC Asserted Delay t
29
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2
In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read During Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0011
DIVSCLK[0] 0101 Unit
SYNC to SCLK First Edge Delay Minimum t
18
4202020 ns
Internal SCLK Period Minimum t
19
25 50 100 200 ns
Internal SCLK Period Maximum t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
15 25 50 100 ns
Internal SCLK LOW Minimum t
21
9.5 24 49 99 ns
SDOUT Valid Setup Time Minimum t
22
4.5 22 22 22 ns
SDOUT Valid Hold Time Minimum t
23
243090 ns
SCLK Last Edge to SYNC Delay Minimum t
24
360140 300 ns
BUSY HIGH Width Maximum (Warp) t
28
1.5 2 3 5.25 µs
BUSY HIGH Width Maximum (Normal) t
28
1.75 2.25 3.25 5.5 µs
BUSY HIGH Width Maximum (Impulse) t
28
2 2.5 3.5 5.75 µs
C