Datasheet

REV. E
–3–
AD7664
Parameter Conditions Min Typ Max Unit
TEMPERATURE RANGE
8
Specified Performance T
MIN
to T
MAX
–40 +85 °C
NOTES
1
LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In Normal Mode.
5
Tested in Parallel Reading Mode.
6
In Impulse Mode.
7
With all digital inputs forced to OVDD or OGND, respect ively.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 11 AND 12
Convert Pulse Width t
1
5ns
Time between Conversions t
2
1.75/2/2.25 Note 1 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
3
25 ns
BUSY HIGH All Modes Except in t
4
1.5/1.75/2 µs
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time t
8
250 ns
RESET Pulsewidth t
9
10 ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay
2
t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay t
18
4ns
Internal SCLK Period t
19
40 75 ns
Internal SCLK HIGH (INVSCLK Low)
3
t
20
30 ns
Internal SCLK LOW (INVSCLK Low)
3
t
21
9.5 ns
SDOUT Valid Setup Time t
22
4.5 ns
SDOUT Valid Hold Time t
23
3ns
SCLK Last Edge to SYNC Delay t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert t
28
2.75/3/3.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay t
29
1/1.25/1.5 µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t
30
50 ns
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
2
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.