Datasheet

REV. E
–16–
AD7664
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
CS = 0
CNVST,
RD
BUSY
DATABUS
Figure 15. Slave Parallel Data Timing for Reading
(Read during Convert)
SERIAL INTERFACE
The AD7664 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7664 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7664 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7664
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted, if desired. Depending on RDC/SDIN input,
the data can be read after each conversion or during the fol-
lowing conversion. Figures 16 and 17 show the detailed timing
diagrams of these two modes.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
123 141516
D15 D14 D2 D1 D0
X
EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
25
t
30
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT
= 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15 D14 D2 D1 D0X
12 3 141516
t
18
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)