Datasheet

REV. B
AD7663
–4–
TIMING SPECIFICATIONS (continued)
Parameter Symbol Min Typ Max Unit
Refer to Figures 17 and 18 (Master Serial Interface Modes)
1
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert t
28
See Table II µs
CNVST LOW to SYNC Asserted Delay t
29
1.25 µs
(Master Serial Read after Convert)
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
I
OH
500A
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing
t
DELAY
t
DELAY
0.8V
0.8V 0.8V
2V2V
2V
Figure 2. Voltage Reference Levels for Timing
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0011
DIVSCLK[0] 0101 Unit
SYNC to SCLK First Edge Delay Minimum t
18
4202020 ns
Internal SCLK Period Minimum t
19
25 50 100 200 ns
Internal SCLK Period Maximum t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
15 25 50 100 ns
Internal SCLK LOW Minimum t
21
9.5 24 49 99 ns
SDOUT Valid Setup Time Minimum t
22
4.5 22 22 22 ns
SDOUT Valid Hold Time Minimum t
23
243090 ns
SCLK Last Edge to SYNC Delay Minimum t
24
360140 300 ns
BUSY HIGH Width Maximum t
28
2 2.5 3.5 5.75 µs