Datasheet

REV. B
AD7663
–16–
SAMPLING RATE – SPS
100k
1
POWER DISSIPATION – ␮W
10k
1k
100
10
1
0.1
10 100 1k 10k 100k 1M
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7663 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion is
complete. The CNVST signal operates independently of CS and
RD signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE CONVERT ACQUIRE CONVERT
Figure 11. Basic Conversion Timing
For a true sampling application, the recommended operation of
the CNVST signal is the following.
CNVST must be held HIGH from the previous falling edge of
BUSY and during a minimum delay corresponding to the acquisi-
tion time t
8
. Then, when CNVST is brought LOW, a conversion is
initiated and the BUSY signal goes HIGH until the completion
of the conversion. Although CNVST is a digital signal, it should
be designed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing. It is a good
thing to shield the CNVST trace with ground and also to add a
low value serial resistor (i.e., 50 W) termination close to the output
of the component that drives this line. For applications where
the SNR is critical, the CNVST signal should have a very low
jitter. To achieve this, some use a dedicated oscillator for
CNVST generation, or at least to clock it with a high frequency,
low jitter clock as shown in Figure 5.
For other applications, conversions can be automatically initiated.
If CNVST is held low when BUSY is low, the AD7663 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7663 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7663 could sometimes
run slightly faster than the guaranteed limit of 250 kSPS.
t
9
t
8
RESET
DATA BUS
BUSY
CNVST
Figure 12. RESET Timing
DIGITAL INTERFACE
The AD7663 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7663 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7663
to the host system interface digital supply. Finally, by using the
OB/2C input pin, twos complement and straight binary coding
can be used.
The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7663 in
multicircuit applications and is held LOW in a single AD7663
design. RD is generally used to enable the conversion result on
the data bus.
t
1
t
3
t
4
t
11
CNVST
BUSY
DATA BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)