Datasheet

AD7661
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7661 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by
CS
. When
CS
and
RD
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7661 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
While the AD7661 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7661 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
SCLK
SDOUT
D15 D14 D1
D0
D13
X15 X14 X13 X1 X0 Y15 Y14
BUSY
SDIN
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
X15 X14
X
1 2 3 14151617 18
t
34
03033-0-034
EXT/INT = 1
RD
RD = 0
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
S
DOUT
SCLK
D1
D0
X
D15 D14 D13
123 141516
t
3
t
35
t
36
t
37
t
31
t
32
t
16
BUSY
EXT/INT = 1 INVSCLK = 0
03033-0-035
CNVST
CS
RD = 0
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)