Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 48

16-Bit 100 kSPS PulSAR

Unipolar ADC with Reference

AD7661

Rev. 0

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FEATURES

2.5 V internal reference: typical drift 3 ppm/°C

Guaranteed max drift 15 ppm/°C

Throughput: 100 kSPS

INL: ±2.5 LSB max (±0.0038% of full scale)

16-bit resolution with no missing codes

S/(N+D): 88 dB min @ 20 kHz

THD: –96 dB max @ 20 kHz

Analog input voltage range: 0 V to 2.5 V

Both AC and DC specifications

No pipeline delay

Parallel and serial 5 V/3 V interface

SPI

®/QSPI

/MICROWIRE

/DSP compatible

Single 5 V supply operation

Power dissipation

16 mW typ, 160 µW @ 1 kSPS without REF

40 mW typ with REF

48-lead LQFP and 48-lead LFCSP packages

Pin-to-pin compatible with PulSAR ADCs

APPLICATIONS

Data acquisition

Medical instruments

Digital signal processing

Spectrum analysis

Instrumentation

Battery-powered systems

Process control

GENERAL DESCRIPTION

The AD7661 is a 16-bit, 100 kSPS, charge redistribution SAR

analog-to-digital converter that operates from a single 5 V

power supply. The part contains a high speed 16-bit sampling

ADC, an internal conversion clock, internal reference, error

correction circuits, and both serial and parallel system inter-

face ports. The AD7661 is hardware factory-calibrated and

comprehensively tested to ensure ac parameters such as signal-

to-noise ratio (SNR) and total harmonic distortion (THD), in

addition to the more traditional dc parameters of gain, offset,

and linearity.

The AD7661 is available in a 48-lead LQFP and a tiny 48-lead

LFCSP with operation specified from –40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

03033-0-001

SWITCHED

CAP DAC

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CLOCK

AD7661

DATA[15:0]

BUSY

SER/PAR

OB/2C

OGND

OVDD

DGNDDVDD

AVDD

AGND

REF REFGND

INGND

RESET

SERIAL

PORT

PARALLEL

INTERFACE

CNVST

REF

REFBUFIN

PDBUF

PDREF

BYTESWAP

Figure 1. Functional Block Diagram

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

800–

1000

Pseudo-

Differential

AD7651

AD7660/AD7661

AD7650/AD7652

AD7664/AD7666

AD7653

AD7667

True Bipolar AD7663 AD7665 AD7671

True

Differential

AD7675 AD7676 AD7677

18-Bit AD7678 AD7679 AD7674

Multichannel/

Simultaneous

AD7654

AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7661 is a 100 kSPS, charge redistribution, 16-bit

SAR ADC with internal error correction circuitry.

2. Superior INL.

The AD7661 has a maximum integral nonlinearity of

2.5 LSB with no missing 16-bit codes.

3. Internal Reference.

The AD7661 has an internal reference with a typical

temperature drift of 3 ppm/°C.

4. Single-Supply Operation.

The AD7661 operates from a single 5 V supply. Its power

dissipation decreases with throughput.

5. Serial or Parallel Interface.

Versatile parallel or 2-wire serial interface arrangement is

compatible with both 3 V and 5 V logic.

Summary of content (28 pages)

PAGE 1
6-Bit 100 kSPS PulSAR® Unipolar ADC with Reference AD7661 2.5 V internal reference: typical drift 3 ppm/°C Guaranteed max drift 15 ppm/°C Throughput: 100 kSPS INL: ±2.5 LSB max (±0.0038% of full scale) 16-bit resolution with no missing codes S/(N+D): 88 dB min @ 20 kHz THD: –96 dB max @ 20 kHz Analog input voltage range: 0 V to 2.
PAGE 2
AD7661 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Interface.......................................................................... 22 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 22 Absolute Maximum Ratings............................................................
PAGE 3
AD7661 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.
PAGE 4
AD7661 Parameter DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format5 Pipeline Delay6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD8 AVDD9 DVDD10 OVDD10 Power Dissipation without REF10 Power Dissipation with REF10 TEMPERATURE RANGE11 Specified Performance Conditions Min Typ –0.3 2.0 –1 –1 ISINK = 1.6 mA ISOURCE = –500 µA 100 kSPS Throughput With Reference and Buffer Reference and Buffer Alone 5 5 6.2 3 1.
PAGE 5
AD7661 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.
PAGE 6
AD7661 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY HIGH Width Maximum Symbol t18 t19 t19 t20 t21 t22 t23 t24 t24 Rev. 0 | Page 6 of 28 0 0 3 25 40 12 7 4 2 3 2 0 1 17 50 70 22 21 18 4 55 2.
PAGE 7
AD7661 ABSOLUTE MAXIMUM RATINGS Table 5. AD7661 Stress Ratings1 1.6mA TO OUTPUT PIN IOL 1.4V CL 60pF* ±0.3 V 500µA IOH * IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. –0.3 V to +7 V ±7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V ±20 mA 700 mW 2.5 W 150°C –65°C to +150°C 300°C 03033-0-002 Rating AVDD + 0.3 V to AGND – 0.3 V Figure 2.
PAGE 8
AD7661 REFGND REF INGND AGND NC AGND AVDD IN TEMP REFBUFIN PDREF PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 36 AGND PIN 1 IDENTIFIER 35 CNVST NC 3 BYTESWAP 4 34 PD 33 RESET OB/2C 5 NC 6 32 CS AD7661 31 RD TOP VIEW (Not to Scale) NC 7 SER/PAR 8 30 DGND 29 BUSY D0 9 28 D15 D1 10 D2/DIVSCLK0 11 27 D14 26 D13 D3/DIVSCLK1 12 03033-0-004 D11/RDERROR D9/SCLK D10/SYNC D8/SDOUT DVDD DGND OVDD OGND D7/RDC/SDIN D4/EXT/INT D5
PAGE 9
AD7661 Pin No. 16 Mnemonic D7 or RDC/SDIN Type1 DI/O 17 18 19 20 21 OGND OVDD DVDD DGND D8 or SDOUT P P P P DO 22 D9 or SCLK DI/O 23 D10 or SYNC DO 24 D11 or RDERROR DO 25–28 D[12:15] DO 29 BUSY DO 30 31 32 DGND RD CS P DI DI 33 RESET DI 34 PD DI 35 CNVST DI 37 38 39 REF REFGND INGND AI/O AI AI Description When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
PAGE 10
AD7661 Pin No. 43 45 46 47 Mnemonic IN TEMP REFBUFIN PDREF Type1 AI AO AI/O DI 48 PDBUF DI Description Primary Analog Input with a Range of 0 V to 2.5 V. Temperature Sensor Voltage Output. Reference Input Voltage. The reference output and the reference buffer input. This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used.
PAGE 11
AD7661 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Aperture Delay Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
PAGE 12
AD7661 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 2.5 2.0 1.0 1.5 1.0 DNL (LSB) INL (LSB) 0.5 0 –0.5 0.5 0 –1.0 03033-0-005 –2.0 –2.5 0 16384 32768 49152 03033-0-008 –0.5 –1.5 –1.0 0 65536 16384 Figure 5. Integral Nonlinearity vs. Code 49152 65536 Figure 8. Differential Nonlinearity vs. Code 40 40 30 30 NUMBER OF UNITS 20 10 20 03033-0-006 10 0 0.0 0.5 1.0 1.5 POSITIVE INL (LSB) 2.0 0 –2.5 2.5 Figure 6.
PAGE 13
AD7661 180000 140000 160000 116740 117518 120000 140000 134409 100000 80000 COUNTS COUNTS 120000 60000 100000 80000 61586 56132 60000 40000 370 81 0 0 20000 59 0 0 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 5181 7FFC 7FFD 7FFE 7FFF CODE IN HEX 8004 120 THD, HARMONICS (dB) –60 –80 –100 –120 –140 SFDR –80 100 –85 90 –90 80 –95 70 60 –100 THD 50 –105 –110 –160 0 10 20 30 FREQUENCY (kHz) 40 THIRD HARMONIC –115 50 1 10 20 1000 100 FREQUENCY (kHz) 15.
PAGE 14
AD7661 S/[N+D] 88 ENOB (Bits) SNR 14.5 ENOB 86 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 03033-0-017 14.0 87 13.5 125 105 5 4 3 FULL-SCALE ERROR 2 1 0 –1 ZERO ERROR –2 –3 –4 03033-0-039 ZERO ERROR, FULL-SCALE ERROR (LSB) 15.0 89 –5 –6 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 20. Zero Error, Full Scale Error with Reference vs. Temperature Figure 17. SNR, S/(N+D), and ENOB vs. Temperature 2.5015 –100 –105 2.
PAGE 15
AD7661 50 OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25°C 40 30 25 OVDD = 5V @ 85°C 20 OVDD = 5V @ 25°C 15 10 03033-0-041 t12 DELAY (ns) 35 5 0 0 50 100 150 200 CL (pF) Figure 23. Typical Delay vs. Load Capacitance CL Rev.
PAGE 16
AD7661 CIRCUIT INFORMATION IN REF REFGND MSB 32,768C 16,384C LSB 4C 2C C SWA SWITCHES CONTROL C BUSY CONTROL LOGIC INGND OUTPUT CODE 65,536C SWB CNVST 03033-0-020 COMP Figure 24. ADC Simplified Schematic The AD7661 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (ADC). The AD7661 is capable of converting 100,000 samples per second (100 kSPS) and allows power savings between conversions.
PAGE 17
AD7661 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7661 offers two output codings: straight binary and twos complement. The LSB size is VREF/65536, which is about 38.15 µV. The AD7661’s ideal transfer characteristic is shown in Figure 25 and Table 7. Description FSR –1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 LSB = V REF /65536 111...111 111...110 111...
PAGE 18
AD7661 TYPICAL CONNECTION DIAGRAM Figure 26 shows a typical connection diagram for the AD7661. Analog Input Figure 27 shows an equivalent circuit of the input structure of the AD7661. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward-biased and start conducting current.
PAGE 19
AD7661 • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7661. The noise coming from the driver is filtered by the AD7661 analog input circuit 1-pole low-pass filter made by R1 and C2 or by the external filter, if one is used. The SNR degradation due to the amplifier is SNRLOSS ⎛ ⎜ 28 = 20 log ⎜ ⎜ π ⎜ 784 + f −3dB (Ne N ) 2 2 ⎝ N is the noise factor of the amplifier (+1 in buffer configuration).
PAGE 20
AD7661 90 For applications that use multiple AD7661s, it is more effective to use the internal buffer to buffer the reference voltage. 80 EXT REF Care should be taken with the voltage reference’s temperature coefficient, which directly affects the full-scale accuracy if this parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. PSRR (dB) 70 Note that VREF can be increased to AVDD – 1.85 V.
PAGE 21
AD7661 CONVERSION CONTROL t2 CNVST BUSY t4 t3 Conversions can be automatically initiated with the AD7661. If CNVST is held LOW when BUSY is LOW, the AD7661 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST LOW, the AD7661 keeps the conversion process running by itself. It should be noted that the analog input must be settled when BUSY goes LOW. Also, at power-up, CNVST should be brought LOW once to initiate the conversion process.
PAGE 22
AD7661 DIGITAL INTERFACE CS The two signals, CS and RD, control the interface. CS and RD have a similar effect because they are OR’d together internally. When at least one of these signals is HIGH, the interface outputs are in high impedance. Usually CS allows the selection of each AD7661 in multicircuit applications and is held low in a single AD7661 design. RD is generally used to enable the conversion result on the data bus.
PAGE 23
AD7661 MASTER SERIAL INTERFACE Usually, because the AD7661 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. This makes the Master Read After Conversion the most recommended serial mode when it can be used. In this mode, it should be noted that unlike in other modes, the BUSY signal returns LOW after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width.
PAGE 24
AD7661 SLAVE SERIAL INTERFACE External Clock The AD7661 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held HIGH. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both LOW, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock.
PAGE 25
AD7661 External Discontinuous Clock Data Read After Conversion External Clock Data Read During Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 41 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning LOW, the conversion’s result can be read while both CS and RD are LOW.
PAGE 26
AD7661 MICROPROCESSOR INTERFACING The AD7661 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. The AD7661 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7661 to prevent digital noise from coupling into the ADC.
PAGE 27
AD7661 APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES In some applications, it is desirable to use a bipolar or wider analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although the AD7661 has only one unipolar range, simple modifications of input driver circuitry allow bipolar and wider input ranges to be used without any performance degradation. Figure 45 shows a connection diagram that allows this. Component values required and resulting full-scale ranges are shown in Table 8.
PAGE 28
AD7661 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 SEATING PLANE PIN 1 SEATING PLANE 7.00 BSC SQ TOP VIEW 0.20 0.09 (PINS DOWN ) VIEW A 7° 3.5° 0° 0.10 MAX COPLANARITY 25 12 24 13 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 46. 48-Lead Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 0.30 0.23 0.18 37 36 PIN 1 INDICATOR 6.