Datasheet

AD7656-1/AD7657-1/AD7658-1 Data Sheet
Rev. D | Page 26 of 32
The first bit of the conversion result is valid on the first SCLK
falling edge after the
CS
falling edge. The subsequent 15 data
bits are clocked out on the rising edge of the SCLK signal. Data
is valid on the SCLK falling edge. To access each conversion result,
16 clock pulses must be provided to the AD7656-1/AD7657-1/
AD7658-1. Figure 34 shows how a 16-SCLK read is used to
access the conversion results.
V1 V2
CONVST A,
CONVST B,
CONVST C
BUSY
CS
DOUT A
DOUT B
DOUT C
32
V3
V4
V5 V6
SCLK
16
t
QUIET
t
ACQ
t
CONV
07017-030
Figure 32. Serial Interface with Three DOUT Lines
V1
V2
V5
DOUT A
DOUT B
48
V3
V4
V6
SCLK
CS
07017-031
Figure 33. Serial Interface with Two DOUT Lines
BUSY
ACQUISITION CONVERSION ACQUISITION
SCLK
CS
DOUT A,
DOUT B,
DOUT C
DB15 DB14 DB13 DB1 DB0
t
ACQ
t
10
t
CONV
t
2
t
1
t
QUIET
t
21
t
20
t
17
t
16
t
18
t
19
CONVST A,
CONVST B,
CONVST C
07017-032
Figure 34. Serial Read Operation