Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 64

250 kSPS, 6-Channel, Simultaneous

Sampling, Bipolar, 16-/14-/12-Bit ADC

Data Sheet

AD7656-1/AD7657-1/AD7658-1

Rev. D

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FEATURES

Pin and software compatible with AD7656/AD7657/AD7658

featuring reduced decoupling requirements

6 independent ADCs

True bipolar analog inputs

Pin-/software-selectable ranges: ±10 V, ±5 V

Fast throughput rate: 250 kSPS

iCMOS process technology

Low power

140 mW at 250 kSPS with 5 V supplies

High noise performance with wide bandwidth

88 dB SNR at 10 kHz input frequency

On-chip reference and reference buffers

High speed parallel, serial, and daisy-chain interface modes

High speed serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible

Standby mode: 315 µW maximum

64-lead LQFP

APPLICATIONS

Power line monitoring and measuring systems

Instrumentation and control systems

Multiaxis positioning systems

FUNCTIONAL BLOCK DIAGRAM

DGND

REF

CONVST A CONVST B CONVST C

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

CONTROL

LOGIC

BUF

AGND

T/H

CLK

OSC

SER/PAR SEL

DRIVE

STBY

DB8/DOUT A

DB9/DOUT B

DB10/DOUT C

DB6/SCLK

WR/REF

EN/DIS

DATA/

CONTROL

LINES

AD7656-1/AD7657-1/AD7658-1

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

07017-001

Figure 1.

GENERAL DESCRIPTION

The AD7656-1/AD7657-1/AD7658-1

are reduced decoupling pin-

and software-compatible versions of AD7656/AD7657/AD7658.

The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/

14-/12-bit, fast, low power successive approximation ADCs in

a package designed on the iCMOS® process (industrial CMOS).

iCMOS is a process combining high voltage silicon with submicron

CMOS and complementary bipolar technologies. It enables the

development of a wide range of high performance analog ICs

capable of 33 V operation in a footprint that no previous generation

of high voltage parts could achieve. Unlike analog ICs using conven-

tional CMOS processes, iCMOS components can accept bipolar

input signals while providing increased performance, which

dramatically reduces power consumption and package size.

The AD7656-1/AD7657-1/AD7658-1 feature throughput rates

of up to 250 kSPS. The parts contain low noise, wide bandwidth

track-and-hold amplifiers that can handle input frequencies

up to 4.5 MHz.

The conversion process and data acquisition are controlled

using the CONVST signals and an internal oscillator. Three

CONVST pins (CONVST A, CONVST B, and CONVST C)

allow independent, simultaneous sampling of the three ADC

pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed

parallel and serial interface, allowing the devices to interface with

microprocessors or DSPs. When the serial interface is selected,

each part has a daisy-chain feature that allows multiple ADCs to

connect to a single serial interface. The AD7656-1/AD7657-1/

AD7658-1 can accommodate true bipolar input signals in the

±4 × V

REF

and ±2 × V

REF

ranges. Each AD7656-1/AD7657-1/

AD7658-1 also contains an on-chip 2.5 V reference.

PRODUCT HIGHLIGHTS

1. Six 16-/14-/12-bit, 250 kSPS ADCs on board.

2. Six true bipolar, high impedance analog inputs.

3. High speed parallel and serial interfaces.

4. Reduced decoupling requirements and reduced bill of

materials cost compared with the AD7656/AD7657/

AD7658 devices.

Protected by U.S. Patent No. 6,731,232.

Summary of content (32 pages)

PAGE 1
FEATURES Pin and software compatible with AD7656/AD7657/AD7658 featuring reduced decoupling requirements 6 independent ADCs True bipolar analog inputs Pin-/software-selectable ranges: ±10 V, ±5 V Fast throughput rate: 250 kSPS iCMOS process technology Low power 140 mW at 250 kSPS with 5 V supplies High noise performance with wide bandwidth 88 dB SNR at 10 kHz input frequency On-chip reference and reference buffers High speed parallel, serial, and daisy-chain interface modes High speed serial interface SPI/Q
PAGE 2
AD7656-1/AD7657-1/AD7658-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 20 Applications ....................................................................................... 1 Converter Details ....................................................................... 20 Functional Block Diagram .............................
PAGE 3
Data Sheet AD7656-1/AD7657-1/AD7658-1 SPECIFICATIONS AD7656-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for the ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for the ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)2 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance2 Output Coding Max Unit 0.3 × VDRIVE ±10 10 V V µA pF 0.2 ±10 10 V V µA pF 3.1 550 250 µs ns kSPS +16.5 −16.5 5.25 5.25 5.25 V V V V V 18 mA 26 mA ISS (Operational) IDD (Operational) Partial Power-Down Mode 0.25 0.
PAGE 5
Data Sheet AD7656-1/AD7657-1/AD7658-1 AD7657-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for the ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for the ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance2 Output Coding Max Unit Test Conditions/Comments 0.2 ±10 10 V V µA pF ISOURCE = 200 µA ISINK = 200 µA 3.1 550 250 µs ns kSPS +16.5 −16.5 5.25 5.25 5.25 V V V V V 18 mA 26 mA ISS (Operational) IDD (Operational) Partial Power-Down Mode 0.25 0.
PAGE 7
Data Sheet AD7656-1/AD7657-1/AD7658-1 AD7658-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 1 Min Typ Max 73.
PAGE 8
AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance2 Output Coding Max Unit Test Conditions/Comments 0.2 ±10 10 V V µA pF ISOURCE = 200 µA ISINK = 200 µA 3.1 550 250 µs ns kSPS +16.5 −16.5 5.25 5.25 5.25 V V V V V 18 mA 26 mA ISS (Operational) IDD (Operational) Partial Power-Down Mode 0.25 0.
PAGE 9
Data Sheet AD7656-1/AD7657-1/AD7658-1 TIMING SPECIFICATIONS AVCC and DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 PARALLEL INTERFACE tCONVERT tQUIET tACQ t10 t1 tWAKE-UP Limit at tMIN, tMAX VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.
PAGE 10
AD7656-1/AD7657-1/AD7658-1 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5.
PAGE 11
Data Sheet AD7656-1/AD7657-1/AD7658-1 AVCC AGND AGND REFIN/REFOUT REFCAPA AGND REFCAPB AGND REFCAPC 64 63 62 61 60 59 58 AGND AVCC AGND H/S SEL SER/PAR SEL DB15 WR/REFEN/DIS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 48 V6 47 AVCC 3 46 AVCC 4 45 V5 DB10/DOUT C 5 44 AGND DB9/DOUT B 6 43 AGND DB8/DOUT A 7 42 V4 DGND 8 41 AVCC VDRIVE 9 40 AVCC DB7/HBEN/DCEN 10 39 V3 DB6/SCLK 11 38 AGND DB5/DCIN A 12 37 AGND DB4/DCIN B 13 36
PAGE 12
AD7656-1/AD7657-1/AD7658-1 Pin No. 19 Mnemonic CS 20 RD 63 WR/REFEN/DIS 18 BUSY 51 REFIN/REFOUT 61 SER/PAR SEL 17 DB0/SEL A 16 DB1/SEL B 15 DB2/SEL C 14 DB3/DCIN C 13 DB4/DCIN B 12 DB5/DCIN A 11 DB6/SCLK 10 DB7/HBEN/DCEN Data Sheet Description Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and the parallel interface is selected, the output bus is enabled and the conversion result is output on the parallel data bus lines.
PAGE 13
Data Sheet Pin No. 7 Mnemonic DB8/DOUT A 6 DB9/DOUT B 5 DB10/DOUT C 4 DB11 2, 3, 64 DB13, DB12, DB15 1 DB14/REFBUFEN/DIS 28 RESET 27 RANGE 31 30 24 VDD VSS STBY 62 H/S SEL 29 W/B AD7656-1/AD7657-1/AD7658-1 Description Data Bit 8/Serial Data Output A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL A = 1, this pin functions as DOUT A and outputs serial conversion data. Data Bit 9/Serial Data Output B.
PAGE 14
AD7656-1/AD7657-1/AD7658-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 0 –40 –60 –80 1.0 DNL (LSB) –20 –100 0.5 0 –0.5 –120 –1.0 –140 –1.5 07017-004 –160 –180 0 20 40 60 80 100 07017-007 AMPLITUDE (dB) VDD/VSS = ±12V TA = –40°C AVCC/DVCC/VDRIVE = 5V DNL WCP = 0.61LSB 1.5 f = 250kSPS DNL WCN = –0.82LSB SAMPLE 2 × VREF RANGE VDD/VSS = ±15V AVCC/DVCC/VDRIVE = 5V ±10V RANGE INTERNAL REFERENCE TA = 25°C fSAMPLE = 250kSPS fIN = 10kHz SNR = 88.44dB SINAD = 88.43dB THD = –111.66dB –2.
PAGE 15
Data Sheet AD7656-1/AD7657-1/AD7658-1 1.0 –80 VDD/VSS = ±12V 0.8 AVCC/DVCC/VDRIVE = 5V fSAMPLE = 250kSPS 0.6 ±5V RANGE –90 0.4 0.2 THD (dB) INL (LSB) fSAMPLE = 250kSPS TA = 25°C INTERNAL REFERENCE –85 0 –0.2 –0.4 –95 ±10V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V –100 –105 –0.6 0 500 1000 1500 2000 2500 3000 3500 ±5V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V –115 10 4000 CODE 07017-013 –1.0 –110 07017-010 –0.8 100 ANALOG INPUT FREQUENCY (kHz) Figure 10.
PAGE 16
AD7656-1/AD7657-1/AD7658-1 Data Sheet 2.510 2.508 100 fSAMPLE = 250kSPS ±2 × VREF RANGE INTERNAL REFERENCE TA = 25°C fIN = 10kHz 100nF ON VDD AND VSS AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V 80 2.504 PSRR (dB) REFERENCE VOLTAGE (V) 90 2.506 2.502 2.500 70 VSS 60 2.498 VDD 2.496 2.492 –55 –35 –15 5 25 45 65 85 105 40 30 125 07017-019 07017-016 50 2.494 80 130 Figure 16. Reference Voltage vs. Temperature 280 330 380 430 530 480 90 AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V 3.
PAGE 17
Data Sheet AD7656-1/AD7657-1/AD7658-1 95 90 110 85 90 75 fSAMPLE = 250kSPS ±2 × VREF RANGE INTERNAL REFERENCE TA = 25°C fIN = 10kHz 1µF ON AVCC SUPPLY PIN ±100mV SUPPLY RIPPLE AMPLITUDE 80 70 AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE ±2 × VREF RANGE 30kHz ON SELECTED CHANNEL 70 60 0 20 40 60 80 100 120 140 Figure 22. Channel-to-Channel Isolation vs.
PAGE 18
AD7656-1/AD7657-1/AD7658-1 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at a ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
PAGE 19
Data Sheet AD7656-1/AD7657-1/AD7658-1 Figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the AD7656-1/AD7657-1/AD7658-1. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the VDD and VSS supplies of the ADC at a frequency sampled, fSAMPLE, as follows: % FSR %FSR is calculated using the full theoretical span of the ADC.
PAGE 20
AD7656-1/AD7657-1/AD7658-1 Data Sheet THEORY OF OPERATION The AD7656-1/AD7657-1/AD7658-1 are pin- and softwarecompatible, reduced decoupling versions of the AD7656/AD7657/ AD7658 devices. In addition, the AD7656-1/AD7657-1/AD7658-1 are high speed, low power converters that allow the simultaneous sampling of six on-chip ADCs. The analog inputs on the AD7656-1/ AD7657-1/AD7658-1 can accept true bipolar input signals.
PAGE 21
Data Sheet AD7656-1/AD7657-1/AD7658-1 ADC TRANSFER FUNCTION The output coding of the AD7656-1/AD7657-1/AD7658-1 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1⁄2 LSB, 3⁄2 LSB. The LSB size is FSR/65,536 for the AD7656-1, FSR/16,384 for the AD7657-1, and FSR/4096 for the AD7658-1. The ideal transfer characteristic is shown in Figure 26. ADC CODE 011 ... 111 011 ...
PAGE 22
AD7656-1/AD7657-1/AD7658-1 Data Sheet DVCC A N A L OG SUPPLY VOLTAGE 5V + 1µF +9.5V TO +16.5V1 SUPPLY 1µF + + 1µF AGND AVCC DVCC VDD DGND 1µF REFCAPA, B, C AGND 2.5V REF 1µF + REFIN/OUT AD7656-1/ AD7657-1/ AD7658-1 AGND SIX ANALOG INPUTS –9.5V TO –16.
PAGE 23
Data Sheet AD7656-1/AD7657-1/AD7658-1 occurs on any one CONVST pin to initiate a conversion then any further CONVST rising edges on any of the CONVST pins are ignored while BUSY is high. further CONVST rising edges on any of the CONVST pins are ignored while BUSY is high. Data can be read from the AD7656-1/AD7657-1/AD7658-1 via the parallel data bus with standard CS and RD signals (W/B = 0). To read the data over the parallel bus, tie SER/PAR SEL low.
PAGE 24
AD7656-1/AD7657-1/AD7658-1 Data Sheet SOFTWARE SELECTION OF ADCS The H/S SEL pin determines the source of the combination of ADCs that are to be simultaneously sampled. When the H/S SEL pin is logic low, the combination of channels to be simultaneously sampled is determined by the CONVST A, CONVST B, and CONVST C pins. When the H/S SEL pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the DB15 to DB13 control registers.
PAGE 25
Data Sheet AD7656-1/AD7657-1/AD7658-1 CHANGING THE ANALOG INPUT RANGE (H/S SEL = 0) The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the user to select either ±2 × VREF or ±4 × VREF as the analog input range for the six analog inputs. When the H/S SEL pin is low, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion.
PAGE 26
AD7656-1/AD7657-1/AD7658-1 Data Sheet 16 clock pulses must be provided to the AD7656-1/AD7657-1/ AD7658-1. Figure 34 shows how a 16-SCLK read is used to access the conversion results. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 15 data bits are clocked out on the rising edge of the SCLK signal. Data is valid on the SCLK falling edge.
PAGE 27
Data Sheet AD7656-1/AD7657-1/AD7658-1 When reading conversion data back from the AD7656-1/AD7657-1/ AD7658-1 using one/two/three DOUT pins, it is possible to configure the parts to operate in daisy-chain mode by using the DCEN pin. This daisy-chain feature allows multiple AD7656-1/ AD7657-1/AD7658-1 devices to be cascaded together and is useful for reducing the component count and wiring connections. An example connection of two devices is shown in Figure 36.
PAGE 28
AD7656-1/AD7657-1/AD7658-1 Data Sheet CONVERT DIGITAL HOST CONVST CONVST AD7656-1/ AD7657-1/ AD7658-1 SCLK DOUT A DCIN A DOUT B DCIN B AD7656-1/ AD7657-1/ AD7658-1 SCLK CS DOUT A DATA IN1 DOUT B DATA IN2 CS CS 07017-033 SCLK DCEN = 0 DEVICE 2 DCEN = 1 DEVICE 1 Figure 36.
PAGE 29
Data Sheet AD7656-1/AD7657-1/AD7658-1 APPLICATION HINTS Design the printed circuit board (PCB) that houses the AD7656-1/ AD7657-1/AD7658-1 so that the analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. It can be common or split between the digital and analog sections.
PAGE 30
Data Sheet AD7656-1/AD7657-1/AD7658-1 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 33 32 17 0.08 COPLANARITY VIEW A VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 40.
PAGE 31
Data Sheet AD7656-1/AD7657-1/AD7658-1 NOTES Rev.
PAGE 32
AD7656-1/AD7657-1/AD7658-1 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07017-0-3/12(D) Rev.