Datasheet

Data Sheet AD7656-1/AD7657-1/AD7658-1
Rev. D | Page 9 of 32
TIMING SPECIFICATIONS
AV
CC
and DV
CC
= 4.75 V to 5.25 V, V
DD
= 5 V to 16.5 V, V
SS
= −5 V to −16.5 V, V
DRIVE
= 2.7 V to 5.25 V, V
REF
= 2.5 V internal/external,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1
Limit at t
MIN,
t
MAX
Unit Description
V
DRIVE
< 4.75 V V
DRIVE
= 4.75 V to 5.25 V
PARALLEL INTERFACE
t
CONVERT
3 3 µs typ Conversion time, internal clock
t
QUIET
150 150 ns min Minimum quiet time required between bus
relinquish and start of next conversion
t
ACQ
550 550 ns min Acquisition time
t
10
25 25 ns min Minimum CONVST low pulse
t
1
60 60 ns max CONVST high to BUSY high
t
WAKE-UP
2 2 ms max
STBY
rising edge to CONVST rising edge
25 25 µs max Partial power-down mode
PARALLEL READ OPERATION
t
2
0 0 ns min BUSY to
RD
delay
t
3
0 0 ns min
CS
to
RD
setup time
t
4
0 0 ns min
CS
to
RD
hold time
t
5
45 36 ns min
RD
pulse width
t
6
45 36 ns max Data access time after
RD
falling edge
t
7
10 10 ns min Data hold time after
RD
rising edge
t
8
12
12
ns max
Bus relinquish time after
RD
rising edge
t
9
6 6 ns min Minimum time between reads
PARALLEL WRITE OPERATION
t
11
15
15
ns min
WR
pulse width
t
12
0 0 ns min
CS
to
WR
setup time
t
13
5 5 ns min
CS
to
WR
hold time
t
14
5 5 ns min Data setup time before
WR
rising edge
t
15
5 5 ns min Data hold after
WR
rising edge
SERIAL INTERFACE
f
SCLK
18 18 MHz max Frequency of serial read clock
t
16
12 12 ns max Delay from
CS
until DOUTx three-state
disabled
t
17
2
22 22 ns max Data access time after SCLK rising edge/
CS
falling edge
t
18
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
19
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
20
10 10 ns min SCLK to data valid hold time after SCLK
falling edge
t
21
18 18 ns max
CS
rising edge to DOUTx high impedance
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
A buffer is used on the DOUTx pins (Pin 5 to Pin 7) for this measurement.
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
25pF
07017-002
Figure 2. Load Circuit for Digital Output Timing Specifications