Datasheet

AD7656-1/AD7657-1/AD7658-1 Data Sheet
Rev. D | Page 4 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage (V
INH
) 0.7 × V
DRIVE
V
Input Low Voltage (V
INL
) 0.3 × V
DRIVE
V
Input Current (I
IN
) ±10 µA Typically 10 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance (C
IN
)
2
10
pF
LOGIC OUTPUTS
Output High Voltage (V
OH
) V
DRIVE
− 0.2 V I
SOURCE
= 200 µA
Output Low Voltage (V
OL
) 0.2 V I
SINK
= 200 µA
Floating-State Leakage Current ±10 µA
Floating-State Output Capacitance
2
10 pF
Output Coding Twos
complement
CONVERSION RATE
Conversion Time 3.1 µs
Track-and-Hold Acquisition Time
1, 2
550 ns
Throughput Rate 250 kSPS Parallel interface mode only
POWER REQUIREMENTS
V
DD
−5 +16.5 V For the 4 × V
REF
range, V
DD
= 10 V to 16.5 V
V
SS
−5
−16.5
V
For the 4 × V
REF
range, V
SS
= −10 V to −16.5 V
AV
CC
4.75 5.25 V
DV
CC
4.75 5.25 V
V
DRIVE
2.7 5.25 V
I
TOTAL
3
Digital inputs = 0 V or V
DRIVE
Normal Mode—Static 18 mA AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
Normal Mode—Operational 26 mA f
SAMPLE
= 250 kSPS, AV
CC
= DV
CC
= V
DRIVE
= +5.25 V,
V
DD
= +16.5 V, V
SS
= −16.5 V
I
SS
(Operational) 0.25 mA V
SS
= −16.5 V, f
SAMPLE
= 250 kSPS
I
DD
(Operational) 0.25 mA V
DD
= +16.5 V, f
SAMPLE
= 250 kSPS
Partial Power-Down Mode
7
mA
AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
Full Power-Down Mode (
STBY
Pin) 60 µA SCLK on or off, AV
CC
= DV
CC
= V
DRIVE
= +5.25 V,
V
DD
= +16.5 V, V
SS
= −16.5 V
Power Dissipation AV
CC
= DV
CC
= V
DRIVE
= +5.25 V, V
DD
= +16.5 V,
V
SS
= −16.5 V
Normal Mode—Static 94 mW
Normal Mode—Operational 140 mW f
SAMPLE
= 250 kSPS
Partial Power-Down Mode 40 mW
Full Power-Down Mode (
STBY
Pin) 315 µW
1
See the Terminology section.
2
Sample tested during initial release to ensure compliance.
3
Includes I
AVCC
, I
VDD
, I
VSS
, I
VDRIVE
, and I
DVCC
.