Datasheet

AD7655
Rev. B | Page 21 of 28
t
3
BUSY
SYNC
SCLK
SDOUT
1216
31 32
CH A
D14
CH B
D15
CH B
D1
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
21
t
23
t
30
t
36
t
25
t
28
t
32
t
31
t
33
t
34
t
12
17
t
35
t
26
EXT/INT = 0
A/B = 1
CNVST
CS, RD
EOC
03536-028
t
11
t
13
t
10
t
26
t
27
t
22
t
29
CH B
D0
CH A
D0
t
37
CH A
D15
Figure 28. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
24
t
21
t
26
t
27
t
28
t
31
t
33
t
32
t
34
t
30
t
29
t
23
t
22
CH A
D15
X
12
16 1
2
t
25
BUSY
SYNC
SCLK
SDOUT
16
CH B
D15
CH A D0
CH A
D14
CH B
D14
CH B D0
t
10
t
11
t
13
t
12
EXT/INT = 0
A/B = 1
CNVST
CS, RD
EOC
03536-029
Figure 29. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)