Datasheet

AD7653
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Symbol
Min Typ Max Unit
Refer to Figure 26 and Figure 27
Convert Pulse Width
t
1
10 ns
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)
1
t
2
1/1.25/1.5 µs
CNVST
LOW to BUSY HIGH Delay t
3
35 ns
BUSY HIGH All Modes Except Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
t
4
0.75/1/1.25 µs
Aperture Delay
t
5
2 ns
End of Conversion to BUSY LOW Delay
t
6
10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t
7
0.75/1/1.25 µs
Acquisition Time
t
8
250 ns
RESET Pulse Width
t
9
10 ns
Refer to Figure 28, Figure 29, and (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t
10
0.75/1/1.25 µs
DATA Valid to BUSY LOW Delay
t
11
12 ns
Bus Access Request to DATA Valid
t
12
45 ns
Bus Relinquish Time
t
13
5 15 ns
Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay t
14
10 ns
CS
LOW to Internal SCLK Valid Delay
2
t
15
10 ns
CS
LOW to SDOUT Delay t
16
10 ns
CNVST
LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t
17
25/275/525 ns
SYNC Asserted to SCLK First Edge Delay
t
18
3 ns
Internal SCLK Period
3
t
19
25 40 ns
Internal SCLK HIGH
3
t
20
12 ns
Internal SCLK LOW
3
t
21
7 ns
SDOUT Valid Setup Time
3
t
22
4 ns
SDOUT Valid Hold Time
3
t
23
2 ns
SCLK Last Edge to SYNC Delay
3
t
24
3 ns
CS
HIGH to SYNC HI-Z t
25
10 ns
CS
HIGH to Internal SCLK HI-Z t
26
10 ns
CS
HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
3
(Warp Mode/Normal Mode/Impulse Mode)
t
28
See Table 4
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
t
29
0.75/1/1.25 µs
SYNC Deasserted to BUSY LOW Delay
t
30
25 ns
Refer to and (Slave Serial Interface Modes)
2
External SCLK Setup Time
t
31
5 ns
External SCLK Active Edge to SDOUT Delay
t
32
3 18 ns
SDIN Setup Time
t
33
5 ns
SDIN Hold Time
t
34
5 ns
External SCLK Period
t
35
25 ns
External SCLK HIGH
t
36
10 ns
External SCLK LOW
t
37
10 ns
Figure 30
Figure 34 Figure 35
1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read during Convert Mode. See for Serial Master Read after Convert mode. Table 4
Rev. A | Page 5 of 28