Datasheet

AD7653
CURRENT
CONVERSION
BUSY
DATA
BUS
t
12
t
13
02966-0-013
RD
CS
DIGITAL INTERFACE
The AD7653 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel inter-
face. The serial interface is multiplexed on the parallel data bus.
The AD7653 digital interface also accommodates both 3 V and
5 V logic by simply connecting the OVDD supply pin of the
AD7653 to the host system interface digital supply. Finally, by
using the OB/
2C
input pin, both twos complement and straight
binary coding can be used.
The two signals,
CS
and
RD
, control the interface.
CS
and
RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually
CS
allows the selection
of each AD7653 in multicircuit applications and is held LOW in
a single AD7653 design.
RD
is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7653 is configured to use the parallel interface when
SER/
PAR
is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F and
, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
igure 29
Figure 29. Slave Parallel Data Timing for Reading
(Read after Convert Mode)
Figure 30
Figure 30. Slave Parallel Data Timing for Reading
(Read during Convert Mode)
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
BUSY
DATA
BUS
02966-0-014
CNVST,
RD
CS = 0
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in , the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
Figure 31
Figure 31. 8-Bit Parallel Interface
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE
HI-Z
HI-Z
t
12
t
12
t
13
02966-A-025
SERIAL INTERFACE
The AD7653 is configured to use the serial interface when
SER/
PAR
is held HIGH. The AD7653 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
Rev. A | Page 20 of 28