Datasheet

AD7652
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t
18
3 17 17 17 ns
Internal SCLK Period Minimum t
19
25 50 100 200 ns
Internal SCLK Period Maximum t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
12 22 50 100 ns
Internal SCLK LOW Minimum t
21
7 21 49 99 ns
SDOUT Valid Setup Time Minimum t
22
4 18 18 18 ns
SDOUT Valid Hold Time Minimum t
23
2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t
24
3 55 130 290 ns
BUSY HIGH Width Maximum t
24
2 2.5 3.5 5.75 µs
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