Datasheet

AD7652
External Discontinuous Clock Data Read After
Conversion
External Clock Data Read During Conversion
Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both
CS
and
RD
are both LOW, the
result of the previous conversion can be read. The data is shifted
out MSB first with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits must be read
before the current conversion is complete; otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the
host interface to prevent incomplete data reading. There is no
daisy-chain feature in this mode and the RDC/SDIN input
should always be tied either HIGH or LOW.
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both
CS
and
RD
are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.
Figure 34
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage tran-
sients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to
ensure that all the bits are read during the first half of the
conversion phase. It is also possible to begin to read data after
conversion and continue to read the last bits after a new
conversion has been initiated. This allows the use of a slower
clock speed like 14 MHz.
Finally, in this mode only, the AD7652 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired, as, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
. Simultaneous sampling is possible by using a
common
CNVST
signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
Figure 36
Figure 36. Two AD7652s in a Daisy-Chain Configuration
SCLK
SDOUTRDC/SDIN
BUSYBUSY
DATA
OUT
AD7652
#1
(DOWNSTREAM)
BUSY
OUT
SCLK
AD7652
#2
(UPSTREAM)
RDC/SDIN SDOUT
SCLK IN
CNVST IN
02965-0-019
CNVST
CS
CNVST
CS
CS IN
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