Datasheet

AD7652
Usually, because the AD7652 is used with a fast throughput,
Master Read During Conversion is the most recommended
serial mode. In this mode mode, the serial clock and data toggle
at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
MASTER SERIAL INTERFACE
Internal Clock
The AD7652 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held LOW. The
AD7652 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. F and show
the detailed timing diagrams of these two modes.
igure 32
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
Figure 33
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert
In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
t
3
BUSY
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
123 141516
D15 D14 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
25
t
30
02964-0-015
CNVST
CS, RD
EXT/INT = 0
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15 D14 D2 D1 D0X
12 3 141516
t
18
BUSY
SYNC
SCLK
SDOUT
02964-0-016
CNVST
CS, RD
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