Datasheet

AD7652
POWER DISSIPATION VERSUS THROUGHPUT
The
CNVST
trace should be shielded with ground and a low
value serial resistor (i.e., 50
Ω) termination should be added
close to the output of the component that drives this line.
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see ). The AD7652 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
Figure 25
Figure 25. Power Dissipation vs. Sampling Rate
For applications where SNR is critical, the
CNVST
signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for
CNVST
generation, or to clock
CNVST
with a
high frequency, low jitter clock, as shown in . Figure 22
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE CONVERT ACQUIRE CONVERT
02964-0-011
CNVST
SAMPLE RATE (SPS)
10
02965-0-037
1000000100 10000 100000
1000
10000
100
1000
100000
10
POWER DISSIPATION (
µ
W)
PDREF = PDBUF = HIGH
CONVERSION CONTROL
Figure 26
Figure 26. Basic Conversion Timing
t
9
t
8
RESET
DATA
BUSY
02964-0-011
CNVST
shows the detailed timing diagrams of the conversion
process. The AD7652 is controlled by the
CNVST
signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete.
CNVST
operates independently of
CS
and
RD
.
Figure 27. RESET Timing
Conversions can be automatically initiated with the AD7652. If
CNVST
is held LOW when BUSY is LOW, the AD7652 controls
the acquisition phase and automatically initiates a new
conversion. By keeping
CNVST
LOW, the AD7652 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up,
CNVST
should be brought LOW once to initiate the
conversion process. In this mode, the AD7652 can run slightly
faster than the guaranteed 500 kSPS.
t
1
t
3
t
4
t
11
BUSY
DATA
BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA NEW DATA
02964-0-012
CNVST
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
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